----------------------------------------------------------------------------------
-- Company:  INFN Sez. di Padova
-- Engineer: Isocrate R.
-- 
-- Create Date:    10:14:34 01/29/2007 
-- Design Name: 
-- Module Name:    Jtag_Switch_Top - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Jtag_Switch_Top is
    Port ( Tck_Port 		: out  STD_LOGIC_VECTOR (6 downto 0);
           Tms_Port 		: out  STD_LOGIC_VECTOR (6 downto 0);
           Tdi_Port 		: out  STD_LOGIC_VECTOR (6 downto 0);
           Tdo_Port 		: in   STD_LOGIC_VECTOR (6 downto 0);
           Init_Port 	: out  STD_LOGIC_VECTOR (6 downto 0);
--           Port0_conf 	: in   STD_LOGIC_VECTOR (1 downto 0);
--           Port1_conf 	: in   STD_LOGIC_VECTOR (1 downto 0);
--           Port2_conf 	: in   STD_LOGIC_VECTOR (1 downto 0);
--           Port3_conf 	: in   STD_LOGIC_VECTOR (1 downto 0);
--           Port4_conf 	: in   STD_LOGIC_VECTOR (1 downto 0);
--           Port5_conf 	: in   STD_LOGIC_VECTOR (1 downto 0);
--           Port6_conf 	: in   STD_LOGIC_VECTOR (1 downto 0);
--           Port0_Sel 	: out  STD_LOGIC_VECTOR (1 downto 0);
--           Port1_Sel 	: out  STD_LOGIC_VECTOR (1 downto 0);
--           Port2_Sel 	: out  STD_LOGIC_VECTOR (1 downto 0);
--           Port3_Sel 	: out  STD_LOGIC_VECTOR (1 downto 0);
--           Port4_Sel 	: out  STD_LOGIC_VECTOR (1 downto 0);
--           Port5_Sel 	: out  STD_LOGIC_VECTOR (1 downto 0);
--           Port6_Sel 	: out  STD_LOGIC_VECTOR (1 downto 0);
--           En_Sel_Port 	: out  STD_LOGIC_VECTOR (6 downto 0);
			  
			  Rmt_Loc		: in   STD_LOGIC;
           Loc_Tms 		: in   STD_LOGIC;
           Loc_Tck 		: in   STD_LOGIC;
           Loc_Tdi 		: in   STD_LOGIC;
           Loc_Tdo 		: out  STD_LOGIC;
           Loc_Init 		: in   STD_LOGIC;
           Rmt_Tck 		: in   STD_LOGIC;
           Rmt_Tms 		: in   STD_LOGIC;
           Rmt_Tdi 		: in   STD_LOGIC;
           Rmt_Tdo 		: out  STD_LOGIC;
           Rmt_Init 		: in   STD_LOGIC
			  
--           Rot_Sw 		: in   STD_LOGIC_VECTOR (3 downto 0);
--           Led 			: out  STD_LOGIC_VECTOR (4 downto 0);
--           Sys_Clock 	: in   STD_LOGIC;
--           I2C_Scl 		: in   STD_LOGIC;
--           I2C_Sda 		: inout  STD_LOGIC;
--           Master_Reset : in   STD_LOGIC);
--			  Picmg0_I2C_Scl 		: in     STD_LOGIC;
--           Picmg0_I2C_Sda 		: inout  STD_LOGIC;
--			  Picmg1_I2C_Scl 		: in     STD_LOGIC;
--           Picmg1_I2C_Sda 		: inout  STD_LOGIC;
--			  Picmg_Addr 		   : in   STD_LOGIC_VECTOR (7 downto 0);
);
end Jtag_Switch_Top;

architecture Behavioral of Jtag_Switch_Top is

-- I2C Slave address
--
-- constant I2C_ADR = 7'h27;

-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--
-- Port register layout (6 regs)
--   
-- Bit <1..0>    Read     Conf Register  11    ---> Board not present (Bypass)
--                                       10    ---> CMC Type 2 (GTS)
--                                       01    ---> CMC Type 1 (Core)
--                                       00    ---> CMC Type 0 (Segment)
-- Bit <3..2>    Write    Sel code register
-- Bit 4         Write    Sel code Enable
-- Bit 5         Write    Force Init 
-- Bit 6         Write    Bypass port 
-- 
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
constant SEL_CODE_ENABLE : integer := 4;
constant FORCE_INIT      : integer := 5;
constant BYPASS          : integer := 6;

type	   type_regs is array (0 to 6) of std_logic_vector ( 7 downto 0 ) ;
signal	I2C_Registers	: type_regs ;

-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

--component I2C_Slave
--	generic Base_Slave_Address : std_logic_vector (7 downto 0);
--port
--(	clock				: in std_logic ;
--	aclr				: in std_logic ;
--	Sck				: in std_logic ;
--	Sda				: inout std_logic_vector ;
--	Byte_Ready		: in std_logic ;
--	Byte_receive	: out std_logic_vector ( 7 downto 0);
--	Byte_send		: in std_logic_vector  ( 7 downto 0);
--	Write				: out std_logic ;
--	Read				: in std_logic 
--);
--end component;

Signal Tck_Int, Tms_Int, Tdi_Int, Tdo_Int, Init_Int : std_logic ;
Signal Td : std_logic_vector  ( 7 downto 0) := "00000000" ;

begin

-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Combinatorial logic

Erase_Regs : for K in 0 to 6 generate	
begin	
	I2C_Registers(K) <= (others => '0');
end generate Erase_Regs ;

Init_Int<= Loc_Init when Rmt_Loc = '1' else Rmt_Init ; 
Tdi_Int <= Loc_Tdi  when Rmt_Loc = '1' else Rmt_Tdi  ; 
Tck_Int <= Loc_Tck  when Rmt_Loc = '1' else Rmt_Tck  ; 
Tms_Int <= Loc_Tms  when Rmt_Loc = '1' else Rmt_Tms  ; 
Loc_Tdo <= Tdo_Int  when Rmt_Loc = '1' else '0';
Rmt_Tdo <= Tdo_Int  when Rmt_Loc = '0' else '0';

Td(0)   <= Tdi_Int ;
Tdo_Int <= Td(7);

Common_Sig_Mpx : for K in 0 to 6 generate	
begin
	
	Init_Port(K) <= Init_int and not I2C_Registers(K)(BYPASS); 
	Tck_Port(K)  <= Tck_int  and not I2C_Registers(K)(BYPASS);
	Tms_Port(K)  <= Tms_int  and not I2C_Registers(K)(BYPASS);
   
	Tdi_Port(K)  <= Td(K)       and not I2C_Registers(K)(BYPASS);
	Td(K+1)      <= Tdo_Port(K) and not I2C_Registers(K)(BYPASS);

end generate Common_Sig_Mpx ;

 
end Behavioral;