----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    19:12:24 01/29/2007 
-- Design Name: 
-- Module Name:    I2C_Module - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity I2C_Module is
    Port ( SysClock : in  STD_LOGIC;
           Aclear : in  STD_LOGIC;
           Sck : in  STD_LOGIC;
           Sda : inout  STD_LOGIC;
           Address : in  STD_LOGIC_VECTOR (7 downto 0);
           Byte_Received : out  STD_LOGIC_VECTOR (7 downto 0));
end I2C_Module;

architecture Behavioral of I2C_Module is

begin


end Behavioral;