Global Data


 

--        Packages Used

ieee.STD_LOGIC_1164
ieee.STD_LOGIC_SIGNED
ieee.NUMERIC_STD
 

--        Interface

bclk : in std_logic ;
lreset : in std_logic ;
l_trg : in std_logic_vector (1 downto 0);
l_tag : in std_logic_vector (7 downto 0);
tag : out std_logic_vector (15 downto 0); -- Registered Output: Yes
strobe : out std_logic ;
ack : in std_logic ;
clear_idle : out std_logic ;
 

--        Controls

Initial State: S0
-------------------
Machine:         Synchronous
Clock:           bclk
Clock Enable:    -
Clock Polarity:  Rising
Reset:           lreset
Reset Mode:      Synchronous
Reset State:     S0
Reset Polarity:  High
State Transition Process:   Synchronous
State Selection:  Case
Transition Selection:  If
     
 

--        Current State


Current Signal Name: visual_S0_current
Next Signal Name: visual_S0_next
Type: enumeration
Hierarchy Mode: Flat
Encoding: User Defined
S0          =>   
S1          =>   
S2          =>   
S3          =>   
S5          =>   
S6          =>   
S7          =>   
S8          =>   
S9          =>   
 

--        States and Transitions

 
Initial State: S0
-------------------
 
State: S0
Enter Action:
  strobe <='0';
  tag<=(others => '0');
Transitions of state S0:
T0 to S0
T1 to S5
  Guard:
    l_trg(0)='1'
 
State: S1
Enter Action:
  tag(15 downto 8) <= l_tag;
Transitions of state S1:
T2 to S2
 
State: S2
Enter Action:
  tag(7 downto 0) <= l_tag;
Transitions of state S2:
T3 to S3
 
State: S3
Enter Action:
  strobe <= '1';
Transitions of state S3:
T5 to S0
  Guard:
    ack = '1'
T6 to S3
 
State: S5
Enter Action:
  clear_idle<='1';
Transitions of state S5:
T12 to S6
 
State: S6
Transitions of state S6:
T13 to S7
 
State: S7
Enter Action:
  clear_idle<='0';
Transitions of state S7:
T14 to S9
 
State: S8
Transitions of state S8:
T10 to S1
 
State: S9
Transitions of state S9:
T11 to S8