INFN

MD2S: MARS Detector Digitising System

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For more information contact Călin A. Ur
Last updated: October 1st, 2006


General Description
Data Acquisition System
Event Data Format
Acquisition Control GUI Interface
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General Description

A new generation of very high efficiency high-resolution gamma-ray spectrometers, like AGATA, is being currently developed. The design of these new arrays is based on the innovative idea to use highly-segmented high-purity large-volume germanium detectors and to reconstruct the energy released by the incident gamma rays by means of gamma-ray tracking algorithms. These algorithms are based on the knowledge of the interaction points in the detector to a few mm precision, that is achieved by a sophisticated analysis of the shape of the net and transient signals from the detector segments. To get a good energy resolution these signals must be recorded in a very low noise environment because the total energy released by the gamma rays will often result from adding deposits in several different segments. While in the final readout electronics many operations will be performed in real time by algorithms running on FPGAs, in the development phase, when such algorithms are still to be optimized, it is important to record sufficiently long signal traces for a detailed off-line analysis. Recent developments of high accuracy and fast ADCs has opened the possibility of precise sampling of the pulse shapes and their further digital filtering. Here we describe the pulse shape digital sampling system developed originally for the MARS segmented detector. The system is currently used at the National Laboratories of Gran Sasso within the framework of the GERDA project for the search of neutrinoless double-beta decay in 76Ge. A more complex system, with 40 acquisition channels, is prepared for the characterization of the AGATA segmented detectors at the Padova Section of INFN.


Block Diagram
Figure 1: Block diagram of the digital sampling system.

The basic unit of the system, shown in the Figure 1, consists of a NIM module and a PCI board interconnected through low-noise high-speed LVDS cables. Each such unit can handle up to four analog input signals. The system was designed with high modularity to allow for fast and easy upgrade and repair. The NIM module, shown in Figure 2, is the result of a collaboration between the Padova and Milano Sections of INFN. It consists of a motherboard that contains the common part for all four channels. The analog conditioning circuit was designed as a separate daugtherboard that can be easily plugged in the motherboard; it is meant to ensure the compatibility between the preamplifier (PA) output signals and the fast ADC (FADC) input; it allows for gain modification and offset variation; gain can be changed to some preset values by modifying the configuration of the jumpers on the board while offset can be adjusted continuously through a screw driven regulator from the front panel; the board implements an antialiasing filter that removes frequency components higher than 40 MHz off the analog PA signal to comply with the Nyquist rule.


FADC NIM Module

Figure 2: The digital sampling NIM module.

Signals are then continuously digitized at 100 Msps by a 14 bit Analog Devices FADC AD6645 mounted on a second daughterboard. The main characteristics of the ADC are: input signal range ±1 V differential, integral nonlinearity ±0.5 LSB and differential nonlinearity ±0.25 LSB. The sampling frequency can be controlled by an external clock with frequencies up to 105 MHz; we fixed the sampling frequency to 100 MHz. 

Data readout is controlled by an ALTERA APEX 20K200EFC484 Field Programmable Gate Array (FPGA). The FPGA programming is done in VHDL language from Linux or Windows operated PC's. The FPGA is mounted on a GIII PCI board developed at CERN which can be mounted directly into a PC or in an external PCI extender. Data transfer from the PCI cards to the PC is operated in 32 bit@33 MHz regime allowing for a maximum transfer rate of 132 MB/s. When more than one NIM-PCI system is used, the synchronization of the channels is ensured by a common external clock and a busy signal that stops/starts the acquisition on all channels at the same time.


The dimension of the FPGA allows for the storage of 2048 channels of sampled data for each event. Data digitized continuously are stored in a circular buffer; when a trigger arrives the buffers are frozen and the readout process starts.


The main characteristics of the system are summarized in the following table:
Analog Inputs number of channels 4
range  SE 1V
DIFF ±1V
input coupling  DC 
Trigger external logic NIM one per card
Clock internal 100 MHz
external variable
Flash ADC  Analog Devices AD6645
resolution 14 bit
INL ±0.50 LSB
DNL ±0.25 LSB
input  DIFF ±1V
max. sampling rate 105 MHz
FPGA Altera APEX 20k200EFC484
FPGA k-gates/ch 100
Traces length max. 2048 channels  
Control  i/f NIM/PCI  
Max output rate 6 MB/s  


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Data Acquisition System 

In order to use the digital sampling system MD2S for testing segmented detectors we have developed a data acquisition system with the following functions:

  • setup the acquisition configuration

  • readout data from FPGA

  • store data on hard disk

  • GUI for online control and data analysis

A schematic view of our data acquisition system is presented in Figure 3.

Schema PCI


A trigger signal is produced externally and distributed to all PCI boards (PCIB). This signal stops the acquisition of sampled data in the circular buffers and induces the PCI boards to produce an interrupt to which the PC interrupt handler has to respond. To instruct the handler what actions should be performed when such an interrupt arrives we developed a kernel driver that has to be loaded into kernel prior starting the acquisition. Through this driver one has access to the PCI registers and to the sampled data. The main functions of this driver are: set the active acquisition channels, read the status of the PCI boards, send commands to the PCI boards, read the sampled data and transfer them into the userspace. A user program has to be active to receive the data and store them on disk. This program adds an header to the data file with information about the acquisition system and a trailer for each event.

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Event Data Format

The format of the events written on disk is:

Header
(ASCII)
?MSDAQ01 Data Label
?CHN0003 Number of Channels
?P002048 Number of Sampling Points
?SPR0016    Sample Precision in Bits
?LBT0013    Number of ADC Conversion Bits
?LTR0016    Trailer Length in Bytes
?CH10002 Channel #1 Enable Pattern 000000001
?CH20000    Channel #2 Enable Pattern 0000000000
?CH30001    Channel #3 Enable Pattern 0000000001
?CH40002    Channel #4 Enable Pattern 0000000010
?MHZ0100 Sampling frequency
?RUN0007    Run No.
?ORIGDAT Original data
?U000029    User Comment Length (in bytes)
"Data Conmment with User Comment Text“
"new lines”"........."
up to 512 characters
?ENDHEAD End of Header
Data Block 1st Event Number_of_Channels_Enabled * ........................................... 3
Number_of_Sampling_Points * sizeof(u16) + ........... 2048 * 2
Event_Trailer_Lentgh = ....................................................... 16
Event_Length = ..................................................... 12304 bytes
2nd Event  .................................................................................................
 
Event Trailer 4 x u32 integers = 16 bytes
  #0   irq. counter (32 bits)
  #1   packed date and time (mktime)
  #2   time stamp (32 bits) - synchronization
  #3   end of event = 0xFFFFFFFF

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Acquisition Control GUI Interface

To control the kernel driver and the user program we developed a graphical user interface using the Qt GUI builder. This GUI allows to load/unload the kernel driver, to start/stop the acquisition and to establish criteria for the acquisition (time or data volume presets). It also monitors the quantity of data  acquired and the space left on disk.

The maximum data transfer rate attainable is given by the speed to which one manages to drain the data through the PCI interface in an interrupt--based transfer mode. We measured the maximum transfer rate to be of about 6 MB/s.