-- Module MGT_custom
-- Generated by Xilinx Architecture Wizard
-- VHDL
-- Written for synthesis tool: Synplicity
-- Xilinx Device: XC2VP7-FF672-6

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.all;
-- synopsys translate_on

entity MGT_custom is
    port (
        CONFIGENABLE : in std_logic;
        CONFIGIN : in std_logic;
        ENMCOMMAALIGN : in std_logic;
        ENPCOMMAALIGN : in std_logic;
        ENCHANSYNC : in std_logic;
        LOOPBACK : in std_logic_vector (1 downto 0);
        POWERDOWN : in std_logic;
        REFCLK : in std_logic;
        REFCLK2 : in std_logic;
        REFCLKSEL : in std_logic;
        BREFCLK : in std_logic;
        BREFCLK2 : in std_logic;
        RXN : in std_logic;
        RXP : in std_logic;
        RXPOLARITY : in std_logic;
        RXRESET : in std_logic;
        RXUSRCLK : in std_logic;
        RXUSRCLK2 : in std_logic;
        TXBYPASS8B10B : in std_logic_vector (1 downto 0);
        TXCHARDISPMODE : in std_logic_vector (1 downto 0);
        TXCHARDISPVAL : in std_logic_vector (1 downto 0);
        TXCHARISK : in std_logic_vector (1 downto 0);
        TXDATA : in std_logic_vector (15 downto 0);
        TXFORCECRCERR : in std_logic;
        TXINHIBIT : in std_logic;
        TXPOLARITY : in std_logic;
        TXRESET : in std_logic;
        TXUSRCLK : in std_logic;
        TXUSRCLK2 : in std_logic;
        CHBONDDONE : out std_logic;
        CONFIGOUT : out std_logic;
        RXBUFSTATUS : out std_logic_vector (1 downto 0);
        RXCHARISCOMMA : out std_logic_vector (1 downto 0);
        RXCHARISK : out std_logic_vector (1 downto 0);
        RXCHECKINGCRC : out std_logic;
        RXCLKCORCNT : out std_logic_vector (2 downto 0);
        RXCOMMADET : out std_logic;
        RXCRCERR : out std_logic;
        RXDATA : out std_logic_vector (15 downto 0);
        RXDISPERR : out std_logic_vector (1 downto 0);
        RXLOSSOFSYNC : out std_logic_vector (1 downto 0);
        RXNOTINTABLE : out std_logic_vector (1 downto 0);
        RXREALIGN : out std_logic;
        RXRECCLK : out std_logic;
        RXRUNDISP : out std_logic_vector (1 downto 0);
        TXBUFERR : out std_logic;
        TXKERR : out std_logic_vector (1 downto 0);
        TXN : out std_logic;
        TXP : out std_logic;
        TXRUNDISP : out std_logic_vector (1 downto 0));
end MGT_custom;