----------------------------------------------------
--  
--      VHDL code generated by Visual Elite
--
--  Root of Design:
--  ---------------
--      Unit    Name  :  ENC
--      Library Name  :  GTS_IF
--  
--      Creation Date :  Sun Mar 27 14:40:29 2005
--      Version       :  3.7.1 build 3. Date: Dec 27 2004. License: 2004.12
--  
--  Options Used:
--  -------------
--      Target
--         Language   :  As Is
--         Purpose    :  Synthesis
--         Vendor     :  Design Compiler
--  
--      Style
--         Use Procedures                 :  No
--         Code Destination               :  Combined file
--         Attach Packages                :  No
--         Generate Entity                :  Yes
--         Attach Directives              :  Yes
--         Structural                     :  No
--         Configuration Specification    :  No
--         library name in
--         Configuration Specification    :  No
--         Configuration Declaration      :  None
--         Preserve spacing for free text :  Yes
--         Declaration alignment          :  No
--
----------------------------------------------------
----------------------------------------------------
--  
--  Library Name :  GTS_IF
--  Unit    Name :  ENC
--  Unit    Type :  Text Unit
--  
------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;


entity  ENC  is
port (count : in std_logic_vector (47 downto 0);
      out_pattern : out std_logic_vector (7 downto 0)
);
end;

------------------------------------------
------------------------------------------
-- Date        : Wed Mar 23 16:32:52 2005
--
-- Author      : 
--
-- Company     : 
--
-- Description : 
--
------------------------------------------
------------------------------------------
architecture  increment  of  ENC  is

begin

  combina: process (count)
  
  variable evTmp,tmp : unsigned (47 downto 0);
  variable nib1, nib2 : unsigned (3 downto 0);
  constant b24 : unsigned (23 downto 0) := "111111111111111111111111";
  constant z24 : unsigned (23 downto 0) := "000000000000000000000000";
  constant b12 : unsigned (11 downto 0) := "111111111111";
  constant z12 : unsigned (11 downto 0) := "000000000000";
  constant b6 : unsigned (5 downto 0) := "111111";
  constant z6 : unsigned (5 downto 0) := "000000";
  constant b3 : unsigned (2 downto 0) := "111";
  constant z3 : unsigned (2 downto 0) := "000";
  begin
      nib1 := unsigned(count(3 downto 0));
      if nib1 > 0  then
         tmp := SHIFT_RIGHT(unsigned(count),to_integer(1+3*nib1));
         nib2(2 downto 0) := tmp(2 downto 0);
	 nib2(3) := '0';
      else
         evTmp := SHIFT_RIGHT(unsigned(count),1);
         if (evTmp(23 downto 0) and b24) = z24 then
             evTmp := SHIFT_RIGHT(evTmp,24);
             nib1 := nib1 + 8;
         end if;
         if (evTmp(11 downto 0) and b12) = z12 then
             evTmp := SHIFT_RIGHT(evTmp,12);
             nib1 := nib1 + 4;
         end if;
         if (evTmp(5 downto 0) and b6) = z6 then
             evTmp := SHIFT_RIGHT(evTmp,6);
             nib1 := nib1 + 2;
         end if;
         if (evTmp (2 downto 0) and b3) = z3 then
             evTmp := SHIFT_RIGHT(evTmp,3);
             nib1 := nib1 + 1;
         end if;
         nib2(2 downto 0) := evTmp(2 downto 0);
         nib2(3) := '1';
      end if;
      out_pattern(7 downto 4) < = std_logic_vector(nib2);
      out_pattern(3 downto 0) < = std_logic_vector(nib1);
    end process;

end;