----------------------------------------------------
--  
--      VHDL code generated by Visual Elite
--
--  Design Unit:
--  ------------
--      Unit    Name  :  TS_ENC
--      Library Name  :  GTS_IF
--  
--      Creation Date :  Sun Mar 27 14:41:42 2005
--      Version       :  3.7.1 build 3. Date: Dec 27 2004. License: 2004.12
--  
--  Options Used:
--  -------------
--      Target
--         Language   :  As Is
--         Purpose    :  Synthesis
--         Vendor     :  Design Compiler
--  
--      Style
--         Use Procedures                 :  No
--         Code Destination               :  Combined file
--         Attach Packages                :  No
--         Generate Entity                :  Yes
--         Attach Directives              :  Yes
--         Structural                     :  No
--         Configuration Specification    :  No
--         library name in
--         Configuration Specification    :  No
--         Configuration Declaration      :  None
--         Preserve spacing for free text :  Yes
--         Declaration alignment          :  No
--
----------------------------------------------------
----------------------------------------------------
--  
--  Library Name :  GTS_IF
--  Unit    Name :  TS_ENC
--  Unit    Type :  Block Diagram
--  
------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.NUMERIC_STD.all;
library SYNOPSYS;
use SYNOPSYS.ATTRIBUTES.ALL;
 
 
entity TS_ENC is
  port (
        en_cnt : in std_logic;
        rst_cnt : in std_logic;
        out_pattern : out std_logic_vector(7 downto 0 );
        ocxo_clk : in std_logic
        );
 
 
end TS_ENC;
 
 
use work.all;
architecture TS_ENC of TS_ENC is
 
  constant b12 : unsigned(11 downto 0 ) := "111111111111";
  signal count : std_logic_vector(47 downto 0 );
  component ENC
      port (
            count : in std_logic_vector(47 downto 0 );
            out_pattern : out std_logic_vector(7 downto 0 )
            );
  end component;
  signal visual_C0_cur_state : std_logic_vector(48 - 1 downto 0 );
  signal visual_C0_next_state : std_logic_vector(48 - 1 downto 0 );
  signal visual_C0_next_count : std_logic_vector(48 - 1 downto 0 );
  signal visual_C0_en_state : std_logic_vector(48 - 1 downto 0 );
 
  -- Start Configuration Specification
  -- ++ for all : ENC use entity work.ENC(increment);
  -- End Configuration Specification
 
begin
 
  inst_ENC: ENC
    port map (
              count => count(47 downto 0),
              out_pattern => out_pattern(7 downto 0)
              );
 
 
  count(47 downto 0) < = (visual_C0_cur_state);
 
 
  visual_C0_en_state < = visual_C0_next_count
                       when en_cnt = '1'
                       else visual_C0_cur_state;
 
  visual_C0_next_state < = visual_C0_en_state;
 
  process (ocxo_clk , rst_cnt)
  begin
   if (rst_cnt = '0') then
      visual_C0_cur_state < = (others => '0');
   elsif (ocxo_clk'event and ocxo_clk = '1') then
 
       visual_C0_cur_state < = visual_C0_next_state;
 
  end if;
  end process;
 
  process (visual_C0_cur_state )
  variable plus_minus_one : unsigned(48 - 1 downto 0);
 
  begin
    plus_minus_one :=  "000000000000000000000000000000000000000000000001" ;
    visual_C0_next_count < = std_logic_vector(unsigned(visual_C0_cur_state) + plus_minus_one);
 
  end process;
 
end TS_ENC;