----------------------------------------------------
--  
--      VHDL code generated by Visual Elite
--
--  Design Unit:
--  ------------
--      Unit    Name  :  T_request_ctrl
--      Library Name  :  GTS_IF
--  
--      Creation Date :  Sun Mar 27 14:40:06 2005
--      Version       :  3.7.1 build 3. Date: Dec 27 2004. License: 2004.12
--  
--  Options Used:
--  -------------
--      Target
--         Language   :  As Is
--         Purpose    :  Synthesis
--         Vendor     :  Design Compiler
--  
--      Style
--         Use Procedures                 :  No
--         Code Destination               :  Combined file
--         Attach Packages                :  No
--         Generate Entity                :  Yes
--         Attach Directives              :  Yes
--         Structural                     :  No
--         Configuration Specification    :  No
--         library name in
--         Configuration Specification    :  No
--         Configuration Declaration      :  None
--         IF for state selection         :  No
--         Preserve spacing for free text :  Yes
--         Declaration alignment          :  No
--
----------------------------------------------------
----------------------------------------------------
--  
--  Library Name :  GTS_IF
--  Unit    Name :  T_request_ctrl
--  Unit    Type :  State Machine
--  
------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
library SYNOPSYS;
use SYNOPSYS.ATTRIBUTES.ALL;
 
 
entity T_request_ctrl is
  port (
        T_request_fifo_full : in std_logic;
        trigger_request : in std_logic;
        T_request_fifo_wr_en : out std_logic;
        gclk : in std_logic;
        reset : in std_logic;
        local_trigger : out std_logic;
        local_trigger_bus : out std_logic_vector(7 downto 0 );
        timestamp : in std_logic_vector(47 downto 0 )
        );
 
end T_request_ctrl;
 
 
architecture T_request_ctrl of T_request_ctrl is
 
  signal tstamp : std_logic_vector(47 downto 0 );
 
  type visual_S0_states is (S0, S1, S2, S3, S4, S5, S6, S7);
 
  signal visual_S0_current : visual_S0_states;
  attribute STATE_VECTOR of T_request_ctrl :
            architecture is "visual_S0_current";
 
 
begin
 
 
 
  -- Synchronous process
  T_request_ctrl_S0:
  process (gclk, reset)
  begin
 
    if (reset = '0') then
      local_trigger_bus < = (others => 'X');
      tstamp < = (others => 'X');
      local_trigger < = 'X';
      T_request_fifo_wr_en< ='0';
      visual_S0_current < = S0;
    elsif (gclk'event and gclk = '1') then
 
      case visual_S0_current is
        when S0 =>
          if (trigger_request = '1' and T_request_fifo_full = '0') then
            local_trigger< ='1';
            T_request_fifo_wr_en< ='1';
            tstamp< =timestamp(47 downto 0);
            visual_S0_current < = S1;
          else
            visual_S0_current < = S0;
          end if;
 
        when S1 =>
          local_trigger< ='0';
          T_request_fifo_wr_en< ='0';
          local_trigger_bus< =tstamp(47 downto 40);
          visual_S0_current < = S2;
 
        when S2 =>
          local_trigger_bus< =tstamp(39 downto 32);
          visual_S0_current < = S3;
 
        when S3 =>
          local_trigger_bus< =tstamp(31 downto 24);
          visual_S0_current < = S4;
 
        when S4 =>
          local_trigger_bus< =tstamp(23 downto 16);
          visual_S0_current < = S5;
 
        when S5 =>
          local_trigger_bus< =tstamp(15 downto 8);
          visual_S0_current < = S6;
 
        when S6 =>
          local_trigger_bus< =tstamp(7 downto 0);
          visual_S0_current < = S7;
 
        when S7 =>
          T_request_fifo_wr_en< ='0';
          visual_S0_current < = S0;
 
        when others =>
 
          T_request_fifo_wr_en< ='0';
          visual_S0_current < = S0;
      end case;
    end if;
  end process T_request_ctrl_S0;
 
end T_request_ctrl;