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-- Date        : Sun Mar 20 21:13:01 2005
--
-- Author      : 
--
-- Company     : 
--
-- Description : 
--
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architecture  t_dec  of  t_decode  is

signal current, previous : std_logic_vector(47 downto 0);
begin

  process (bclk,lreset)
  
  variable evNumL,tmp : unsigned (47 downto 0);
  variable nib1,nib2 : std_logic_vector(3 downto 0);
   begin
     if lreset ='1' then
          current < = (others=>'0');
          previous < = (others=>'0');
     elsif (bclk'event and bclk='1') then
          evNumL := unsigned(current);
          nib1 := fiber_in(3 downto 0);
          nib2 := fiber_in(7 downto 4);
          if nib2(3)='1'  then
             evNumL := evNumL and unsigned(msk1);
             tmp := unsigned ("00000000000000000000000000000000000000000000" & (nib2 and "0111"));
             tmp := SHIFT_LEFT(tmp,to_integer(1+3*(unsigned(nib1))));
             evNumL := evNumL or tmp;
          else
             evNumL(3 downto 0) := unsigned(nib1);
             evNumL := evNumL and unsigned(msk2);
             tmp := unsigned ("00000000000000000000000000000000000000000000" & (nib2 and "0111"));
             tmp := SHIFT_LEFT(tmp,to_integer(1+3*(unsigned(nib1))));
             evNumL :=evNumL or tmp;
          end if;
          previous < = current;
          current < = std_logic_vector(evNumL);
          if unsigned(current) = (unsigned(previous)+1) then
            tstamp_err < ='0';
          else
            tstamp_err < ='1';
          end if;
          timestamp < = std_logic_vector(evNumL);
          tstamp_lsw < = std_logic_vector(evNumL(15 downto 0));
      end if;
    end process;
end t_dec;