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--  
--      VHDL code generated by Visual Elite
--
--  Root of Design:
--  ---------------
--      Unit    Name  :  t_decode
--      Library Name  :  GTS_IF
--  
--      Creation Date :  Sun Mar 27 14:41:26 2005
--      Version       :  3.7.1 build 3. Date: Dec 27 2004. License: 2004.12
--  
--  Options Used:
--  -------------
--      Target
--         Language   :  As Is
--         Purpose    :  Synthesis
--         Vendor     :  Design Compiler
--  
--      Style
--         Use Procedures                 :  No
--         Code Destination               :  Combined file
--         Attach Packages                :  No
--         Generate Entity                :  Yes
--         Attach Directives              :  Yes
--         Structural                     :  No
--         Configuration Specification    :  No
--         library name in
--         Configuration Specification    :  No
--         Configuration Declaration      :  None
--         Preserve spacing for free text :  Yes
--         Declaration alignment          :  No
--
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----------------------------------------------------
--  
--  Library Name :  GTS_IF
--  Unit    Name :  t_decode
--  Unit    Type :  Text Unit
--  
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-- Date        : Sun Mar 20 21:13:01 2005
--
-- Author      : 
--
-- Company     : 
--
-- Description : 
--
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;


entity  t_decode  is
port (clk, reset : in std_logic;
      tstamp_err : out std_logic;
      fiber_in : in std_logic_vector (15 downto 0);
      msk1 : in std_logic_vector (47 downto 0);
      msk2 : in std_logic_vector (47 downto 0);
      timestamp : out std_logic_vector (47 downto 0);
      timestamp_lsw : out std_logic_vector (15 downto 0)
);
end;


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-- Date        : Sun Mar 20 21:13:01 2005
--
-- Author      : 
--
-- Company     : 
--
-- Description : 
--
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architecture  t_dec  of  t_decode  is

signal current, previous : std_logic_vector(47 downto 0);
begin

  process (clk,reset)
  
  variable evNumL,tmp : unsigned (47 downto 0);
  variable nib1,nib2 : std_logic_vector(3 downto 0);
   begin
     if reset ='0' then
          current < = (others=>'0');
          previous < = (others=>'0');
     elsif (clk'event and clk='1') then
          evNumL := unsigned(current);
          nib1 := fiber_in(3 downto 0);
          nib2 := fiber_in(7 downto 4);
          if nib2(3)='1'  then
             evNumL := evNumL and unsigned(msk1);
             tmp := unsigned ("00000000000000000000000000000000000000000000" & (nib2 and "0111"));
             tmp := SHIFT_LEFT(tmp,to_integer(1+3*(unsigned(nib1))));
             evNumL := evNumL or tmp;
          else
             evNumL(3 downto 0) := unsigned(nib1);
             evNumL := evNumL and unsigned(msk2);
             tmp := unsigned ("00000000000000000000000000000000000000000000" & (nib2 and "0111"));
             tmp := SHIFT_LEFT(tmp,to_integer(1+3*(unsigned(nib1))));
             evNumL :=evNumL or tmp;
          end if;
          if evNumL /= (unsigned(previous)+1) then
            tstamp_err < ='1';
          else
            tstamp_err < ='0';
          end if;
          previous < = current;
          current < = std_logic_vector(evNumL);
          timestamp < = std_logic_vector(evNumL);
          timestamp_lsw < = std_logic_vector(evNumL(15 downto 0));
      end if;
    end process;
end t_dec;