----------------------------------------------------
--  
--      VHDL code generated by Visual Elite
--
--  Root of Design:
--  ---------------
--      Unit    Name  :  RTX
--      Library Name  :  GTS
--  
--      Creation Date :  Tue Sep 27 09:44:04 2005
--      Version       :  3.8.3 build 14. Date: Aug  4 2005. License: 2005.8
--  
--  Options Used:
--  -------------
--      Target
--         Language   :  As Is
--         Purpose    :  Synthesis
--         Vendor     :  Synplify
--  
--      Style
--         Use Procedures                 :  No
--         Code Destination               :  Combined file
--         Attach Packages                :  No
--         Generate Entity                :  Yes
--         Attach Directives              :  Yes
--         Structural                     :  No
--         Configuration Specification    :  No
--         library name in
--         Configuration Specification    :  No
--         Configuration Declaration      :  None
--         Preserve spacing for free text :  Yes
--         Declaration alignment          :  No
--
----------------------------------------------------
----------------------------------------------------
--  
--  Library Name :  GTS
--  Unit    Name :  L1A_fifo_ctrl
--  Unit    Type :  State Machine
--  
------------------------------------------------------
 
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.STD_LOGIC_SIGNED.all;
use ieee.NUMERIC_STD.all;
library synplify;
use synplify.attributes.all;
 
 
entity L1A_fifo_ctrl is
  port (
        bclk : in std_logic;
        lreset : in std_logic;
        L1A_fifo_wr_en : out std_logic;
        L1A_fifo_full : in std_logic;
        L1A_arrived : in std_logic
        );
 
end L1A_fifo_ctrl;
 
 
architecture L1A_fifo_ctrl of L1A_fifo_ctrl is
 
  type visual_S0_states is (S0, S1);
  signal visual_S0_current : visual_S0_states;
 
 
begin
 
 
 
  -- Synchronous process
  L1A_fifo_ctrl_S0:
  process (bclk, lreset)
  begin
 
    if (lreset = '1') then
      L1A_fifo_wr_en< ='0';
      visual_S0_current < = S0;
    elsif (bclk'event and bclk = '1') then
 
      case visual_S0_current is
        when S0 =>
          if (L1A_arrived = '1' and L1A_fifo_full = '0') then
            L1A_fifo_wr_en< ='1';
            visual_S0_current < = S1;
          else
            visual_S0_current < = S0;
          end if;
 
        when S1 =>
          L1A_fifo_wr_en< ='0';
          visual_S0_current < = S0;
 
        when others =>
 
          L1A_fifo_wr_en< ='0';
          visual_S0_current < = S0;
      end case;
    end if;
  end process L1A_fifo_ctrl_S0;
 
end L1A_fifo_ctrl;
----------------------------------------------------
--  
--  Library Name :  GTS
--  Unit    Name :  Hamming8
--  Unit    Type :  Text Unit
--  
------------------------------------------------------
 -----------------------------------------------------------------------------
   -- This functional block provides the EDAC logic to correct up
   -- to one bit error and to detect up to two bit errors in an
   -- 4-bit input data word. The codewords are 8-bit long.
   -- It is a modified Hamming (8, 4, 4) code featuring
   -- Single Error Correction (SEC) and Double Error Detection (DED).
   --
   -- Two parity bits have been inversed to avoid an all-zero code word.
   -----------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;

entity Hamming8 is
   port(
      DataOut:       in    std_logic_vector(0 to 7) ;               -- Output data bits
      CheckOut:      out   std_logic_vector(0 to 7) ;               -- Output check bits

      DataIn:        in    std_logic_vector(0 to 7) ;               -- Input data bits
      CheckIn:       in    std_logic_vector(0 to 7) ;               -- Input check bits

      DataCorr:      out   std_logic_vector(0 to 7) ;               -- Corrected data bits
      SingleErr:     out   Std_ULogic;          -- Single error
      DoubleErr:     out   Std_ULogic;          -- Double error
      MultipleErr:   out   Std_ULogic          -- Uncorrectable error
   );
end Hamming8;



architecture RTL of Hamming8 is

 begin

   process (DataOut,DataIn,CheckIn)
      variable PgenL,PgenH:         Std_Logic_Vector(0 to 3);  -- Generated parity
      variable SyndL,SyndH:         Std_Logic_Vector(0 to 3);  -- Syndrome
      variable FlipL,FlipH:         Std_Logic_Vector(0 to 3);  -- Bits to invert
      variable ChipL,ChipH:         Std_Logic_Vector(0 to 3);  -- Errors in parity

   begin
      -- Check bit generator
      PgenL(0) := not (DataIn(0) xor DataIn(1) xor DataIn(2));
      PgenL(1) :=      DataIn(0) xor DataIn(1) xor DataIn(3);
      PgenL(2) := not (DataIn(0) xor DataIn(2) xor DataIn(3));
      PgenL(3) :=      DataIn(1) xor DataIn(2) xor DataIn(3);

      PgenH(0) := not (DataIn(4) xor DataIn(5) xor DataIn(6));
      PgenH(1) :=      DataIn(4) xor DataIn(5) xor DataIn(7);
      PgenH(2) := not (DataIn(4) xor DataIn(6) xor DataIn(7));
      PgenH(3) :=      DataIn(5) xor DataIn(6) xor DataIn(7);

      -- Syndrome bit generator
      SyndL(0) := PgenL(0) xor not CheckIn(0);
      SyndL(1) := PgenL(1) xor not CheckIn(1);
      SyndL(2) := PgenL(2) xor     CheckIn(2);
      SyndL(3) := PgenL(3) xor     CheckIn(3);

      SyndH(0) := PgenH(0) xor not CheckIn(4);
      SyndH(1) := PgenH(1) xor not CheckIn(5);
      SyndH(2) := PgenH(2) xor     CheckIn(6);
      SyndH(3) := PgenH(3) xor     CheckIn(7);

      -- Bit corrector
      if SyndL="1110" then
         FlipL(0) := '1';
      else
         FlipL(0) := '0';
      end if;
      if SyndL="1101" then
         FlipL(1) := '1';
      else
         FlipL(1) := '0';
      end if;
      if SyndL="1011" then
         FlipL(2) := '1';
      else
         FlipL(2) := '0';
      end if;
      if SyndL="0111" then
         FlipL(3) := '1';
      else
         FlipL(3) := '0';
      end if;

      if SyndH="1110" then
         FlipH(0) := '1';
      else
         FlipH(0) := '0';
      end if;
      if SyndH="1101" then
         FlipH(1) := '1';
      else
         FlipH(1) := '0';
      end if;
      if SyndH="1011" then
         FlipH(2) := '1';
      else
         FlipH(2) := '0';
      end if;
      if SyndH="0111" then
         FlipH(3) := '1';
      else
         FlipH(3) := '0';
      end if;

      -- Single error in check bits
      if SyndL="0001" then
         ChipL(0) := '1';
      else
         ChipL(0) := '0';
      end if;
      if SyndL="0010" then
         ChipL(1) := '1';
      else
         ChipL(1) := '0';
      end if;
      if SyndL="0100" then
         ChipL(2) := '1';
      else
         ChipL(2) := '0';
      end if;
      if SyndL="1000" then
         ChipL(3) := '1';
      else
         ChipL(3) := '0';
      end if;

      if SyndH="0001" then
         ChipH(0) := '1';
      else
         ChipH(0) := '0';
      end if;
      if SyndH="0010" then
         ChipH(1) := '1';
      else
         ChipH(1) := '0';
      end if;
      if SyndH="0100" then
         ChipH(2) := '1';
      else
         ChipH(2) := '0';
      end if;
      if SyndH="1000" then
         ChipH(3) := '1';
      else
         ChipH(3) := '0';
      end if;

      -- Corrected data
      DataCorr(0) < = DataIn(0) xor FlipL(0);
      DataCorr(1) < = DataIn(1) xor FlipL(1);
      DataCorr(2) < = DataIn(2) xor FlipL(2);
      DataCorr(3) < = DataIn(3) xor FlipL(3);

      DataCorr(4) < = DataIn(4) xor FlipH(0);
      DataCorr(5) < = DataIn(5) xor FlipH(1);
      DataCorr(6) < = DataIn(6) xor FlipH(2);
      DataCorr(7) < = DataIn(7) xor FlipH(3);

      -- Check bits
      CheckOut(0) < = not (not (DataOut(0) xor DataOut(1) xor DataOut(2)));
      CheckOut(1) < = not (     DataOut(0) xor DataOut(1) xor DataOut(3));
      CheckOut(2) < =     (not (DataOut(0) xor DataOut(2) xor DataOut(3)));
      CheckOut(3) < =     (     DataOut(1) xor DataOut(2) xor DataOut(3));

      CheckOut(4) < = not (not (DataOut(4) xor DataOut(5) xor DataOut(6)));
      CheckOut(5) < = not (     DataOut(4) xor DataOut(5) xor DataOut(7));
      CheckOut(6) < =     (not (DataOut(4) xor DataOut(6) xor DataOut(7)));
      CheckOut(7) < =     (     DataOut(5) xor DataOut(6) xor DataOut(7));

      -- Single correctable error flag
      SingleErr   < = (FlipL(0) or FlipL(1) or FlipL(2) or FlipL(3)) xor
                     (FlipH(0) or FlipH(1) or FlipH(2) or FlipH(3)) xor
                     (ChipL(0) or ChipL(1) or ChipL(2) or ChipL(3)) xor
                     (ChipH(0) or ChipH(1) or ChipH(2) or ChipH(3));

      -- double correctable error flag
      DoubleErr   < = ((FlipL(0) or FlipL(1) or FlipL(2) or FlipL(3)) or
                      (ChipL(0) or ChipL(1) or ChipL(2) or ChipL(3))) and

                     ((FlipH(0) or FlipH(1) or FlipH(2) or FlipH(3)) or
                      (ChipH(0) or ChipH(1) or ChipH(2) or ChipH(3)));

      -- Uncorrectable error flag
      if SyndL="0011" or SyndL="0101" or
         SyndL="0110" or SyndL="1001" or
         SyndL="1010" or SyndL="1100" or
         SyndL="1111" or
         SyndH="0011" or SyndH="0101" or
         SyndH="0110" or SyndH="1001" or
         SyndH="1010" or SyndH="1100" or
         SyndH="1111" then
         MultipleErr    < = '1';
      else
         MultipleErr    < = '0';
      end if;

   end process;
 end RTL;



----------------------------------------------------
--  
--  Library Name :  GTS
--  Unit    Name :  ctrl
--  Unit    Type :  State Machine
--  
------------------------------------------------------
 
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.STD_LOGIC_SIGNED.all;
use ieee.NUMERIC_STD.all;
library synplify;
use synplify.attributes.all;
 
 
entity ctrl is
  port (
        backpressure : in std_logic;
        msg_in : in std_logic_vector(7 downto 0 );
        msg_strobe : in std_logic_vector(1 downto 0 );
        bclk : in std_logic;
        lreset : in std_logic;
        tag : in std_logic_vector(15 downto 0 );
        strobe : in std_logic;
        ack : out std_logic;
        DataOut : out std_logic_vector(0 to 7 )
        );
 
end ctrl;
 
 
architecture ctrl of ctrl is
 
  type visual_S0_states is (S0, S1, S2, S5, S6, S7, S8);
  signal visual_S0_current : visual_S0_states;
 
 
begin
 
 
 
  -- Synchronous process
  ctrl_S0:
  process (bclk)
  begin
 
    if (bclk'event and bclk = '1') then
      if (lreset = '1') then
        ack< ='0';
        visual_S0_current < = S0;
      else
 
        case visual_S0_current is
          when S0 =>
            if (strobe = '1') then
              DataOut(0 to 3)< ="1111"; -- start of cmd
              DataOut(4 to 7)< ="0011"; -- cmd length
              visual_S0_current < = S1;
            elsif (backpressure = '1') then
              visual_S0_current < = S2;
            else
              visual_S0_current < = S0;
            end if;
 
          when S1 =>
            DataOut< ="00000001"; -- TRG REQ
            visual_S0_current < = S5;
 
          when S2 =>
            ack< ='0';
            visual_S0_current < = S0;
 
          when S5 =>
            DataOut< = tag(7 downto 0);
            visual_S0_current < = S6;
 
          when S6 =>
            DataOut< =tag(15 downto 8);
            visual_S0_current < = S8;
 
          when S7 =>
            if (strobe = '0') then
              ack< ='0';
              visual_S0_current < = S0;
            else
              visual_S0_current < = S7;
            end if;
 
          when S8 =>
            DataOut< =(others =>'0');
            ack< ='1';
            visual_S0_current < = S7;
 
          when others =>
 
            ack< ='0';
            visual_S0_current < = S0;
        end case;
      end if;
    end if;
  end process ctrl_S0;
 
end ctrl;
----------------------------------------------------
--  
--  Library Name :  GTS
--  Unit    Name :  trg_req_gen
--  Unit    Type :  State Machine
--  
------------------------------------------------------
 
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.STD_LOGIC_SIGNED.all;
use ieee.NUMERIC_STD.all;
library synplify;
use synplify.attributes.all;
 
 
entity trg_req_gen is
  port (
        bclk : in std_logic;
        lreset : in std_logic;
        l_trg : in std_logic_vector(1 downto 0 );
        l_tag : in std_logic_vector(7 downto 0 );
        tag : out std_logic_vector(15 downto 0 );
        strobe : out std_logic;
        ack : in std_logic
        );
 
end trg_req_gen;
 
 
architecture trg_req_gen of trg_req_gen is
 
  type visual_S0_states is (S0, S1, S2, S3);
  signal visual_S0_current : visual_S0_states;
 
 
begin
 
 
 
  -- Synchronous process
  trg_req_gen_S0:
  process (bclk)
  begin
 
    if (bclk'event and bclk = '1') then
      if (lreset = '1') then
        strobe < ='0';
        tag< =(others => '0');
        visual_S0_current < = S0;
      else
 
        case visual_S0_current is
          when S0 =>
            if (l_trg(0) = '1') then
              tag(7 downto 0) < = l_tag;
              visual_S0_current < = S1;
            else
              visual_S0_current < = S0;
            end if;
 
          when S1 =>
            tag(15 downto 8) < = l_tag;
            visual_S0_current < = S2;
 
          when S2 =>
            strobe < = '1';
            visual_S0_current < = S3;
 
          when S3 =>
            if (ack = '1') then
              strobe < ='0';
              tag< =(others => '0');
              visual_S0_current < = S0;
            else
              visual_S0_current < = S3;
            end if;
 
          when others =>
 
            strobe < ='0';
            tag< =(others => '0');
            visual_S0_current < = S0;
        end case;
      end if;
    end if;
  end process trg_req_gen_S0;
 
end trg_req_gen;
----------------------------------------------------
--  
--  Library Name :  GTS
--  Unit    Name :  cmd_enc
--  Unit    Type :  Block Diagram
--  
------------------------------------------------------
 
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.STD_LOGIC_SIGNED.all;
use ieee.NUMERIC_STD.all;
library synplify;
use synplify.attributes.all;
 
 
entity cmd_enc is
  port (
        DoubleErr : out std_ulogic;
        l_tag : in std_logic_vector(7 downto 0 );
        TXDATA : out std_logic_vector(15 downto 0 );
        MultipleErr : out std_ulogic;
        msg_in : in std_logic_vector(7 downto 0 );
        SingleErr : out std_ulogic;
        bclk : in std_logic;
        msg_strobe : in std_logic_vector(1 downto 0 );
        lreset : in std_logic;
        backpressure : in std_logic;
        l_trg : in std_logic_vector(1 downto 0 );
        DataCorr : out std_logic_vector(0 to 7 )
        );
 
 
end cmd_enc;
 
 
use work.all;
architecture cmd_enc of cmd_enc is
 
  signal DataOut : std_logic_vector(0 to 7 );
  signal g : std_logic_vector(0 to 7 );
  signal strobe : std_logic;
  signal tag : std_logic_vector(15 downto 0 );
  signal ack : std_logic;
  signal CheckOut : std_logic_vector(0 to 7 );
  component trg_req_gen
      port (
            bclk : in std_logic;
            lreset : in std_logic;
            l_trg : in std_logic_vector(1 downto 0 );
            l_tag : in std_logic_vector(7 downto 0 );
            tag : out std_logic_vector(15 downto 0 );
            strobe : out std_logic;
            ack : in std_logic
            );
  end component;
  component ctrl
      port (
            backpressure : in std_logic;
            msg_in : in std_logic_vector(7 downto 0 );
            msg_strobe : in std_logic_vector(1 downto 0 );
            bclk : in std_logic;
            lreset : in std_logic;
            tag : in std_logic_vector(15 downto 0 );
            strobe : in std_logic;
            ack : out std_logic;
            DataOut : out std_logic_vector(0 to 7 )
            );
  end component;
  component Hamming8
      port (
            DataOut : in std_logic_vector(0 to 7 );
            CheckOut : out std_logic_vector(0 to 7 );
            DataIn : in std_logic_vector(0 to 7 );
            CheckIn : in std_logic_vector(0 to 7 );
            DataCorr : out std_logic_vector(0 to 7 );
            SingleErr : out std_ulogic;
            DoubleErr : out std_ulogic;
            MultipleErr : out std_ulogic
            );
  end component;
 
  -- Start Configuration Specification
  -- ++ for all : trg_req_gen use entity work.trg_req_gen(trg_req_gen);
  -- ++ for all : ctrl use entity work.ctrl(ctrl);
  -- ++ for all : Hamming8 use entity work.Hamming8(RTL);
  -- End Configuration Specification
 
begin
 
  inst_trg_req_gen: trg_req_gen
    port map (
              bclk => bclk,
              lreset => lreset,
              l_trg => l_trg(1 downto 0),
              l_tag => l_tag(7 downto 0),
              tag => tag(15 downto 0),
              strobe => strobe,
              ack => ack
              );
 
  cmd_enc_ctrl: ctrl
    port map (
              backpressure => backpressure,
              msg_in => msg_in(7 downto 0),
              msg_strobe => msg_strobe(1 downto 0),
              bclk => bclk,
              lreset => lreset,
              tag => tag(15 downto 0),
              strobe => strobe,
              ack => ack,
              DataOut => DataOut(0 to 7)
              );
 
  C0: Hamming8
    port map (
              DataOut => DataOut(0 to 7),
              CheckOut => CheckOut(0 to 7),
              DataIn => g(0 to 7),
              CheckIn => g(0 to 7),
              DataCorr => DataCorr(0 to 7),
              SingleErr => SingleErr,
              DoubleErr => DoubleErr,
              MultipleErr => MultipleErr
              );
 
  TXDATA(15 downto 8) < = CheckOut(0 to 7);
  TXDATA(7 downto 0) < = DataOut(0 to 7);
 
      g(0 to 7) < = (others => '0');
end cmd_enc;
----------------------------------------------------
--  
--  Library Name :  unisim
--  Unit    Name :  gt_swift
--  Unit    Type :  Text Unit
--  
------------------------------------------------------


library ieee;
use ieee.std_logic_1164.all;

entity gt_swift is
	generic (
		TimingVersion: string := "gt_swift";
		DelayRange: string := "MAX";
		MC_Reference: string := "0000"
	);

	port (
		RXP: in std_logic := 'U';
		RXN: in std_logic := 'U';
		TXP: out std_logic;
		TXN: out std_logic;
		REFCLK: in std_logic := 'U';
		REFCLK2: in std_logic := 'U';
		REFCLKSEL: in std_logic := 'U';
		BREFCLK: in std_logic := 'U';
		BREFCLK2: in std_logic := 'U';
		RXUSRCLK: in std_logic := 'U';
		TXUSRCLK: in std_logic := 'U';
		RXUSRCLK2: in std_logic := 'U';
		TXUSRCLK2: in std_logic := 'U';
		RXRESET: in std_logic := 'U';
		TXRESET: in std_logic := 'U';
		POWERDOWN: in std_logic := 'U';
		LOOPBACK_0: in std_logic := 'U';
		LOOPBACK_1: in std_logic := 'U';
		TXDATA_0: in std_logic := 'U';
		TXDATA_1: in std_logic := 'U';
		TXDATA_2: in std_logic := 'U';
		TXDATA_3: in std_logic := 'U';
		TXDATA_4: in std_logic := 'U';
		TXDATA_5: in std_logic := 'U';
		TXDATA_6: in std_logic := 'U';
		TXDATA_7: in std_logic := 'U';
		TXDATA_8: in std_logic := 'U';
		TXDATA_9: in std_logic := 'U';
		TXDATA_10: in std_logic := 'U';
		TXDATA_11: in std_logic := 'U';
		TXDATA_12: in std_logic := 'U';
		TXDATA_13: in std_logic := 'U';
		TXDATA_14: in std_logic := 'U';
		TXDATA_15: in std_logic := 'U';
		TXDATA_16: in std_logic := 'U';
		TXDATA_17: in std_logic := 'U';
		TXDATA_18: in std_logic := 'U';
		TXDATA_19: in std_logic := 'U';
		TXDATA_20: in std_logic := 'U';
		TXDATA_21: in std_logic := 'U';
		TXDATA_22: in std_logic := 'U';
		TXDATA_23: in std_logic := 'U';
		TXDATA_24: in std_logic := 'U';
		TXDATA_25: in std_logic := 'U';
		TXDATA_26: in std_logic := 'U';
		TXDATA_27: in std_logic := 'U';
		TXDATA_28: in std_logic := 'U';
		TXDATA_29: in std_logic := 'U';
		TXDATA_30: in std_logic := 'U';
		TXDATA_31: in std_logic := 'U';
		TXCHARDISPMODE_0: in std_logic := 'U';
		TXCHARDISPMODE_1: in std_logic := 'U';
		TXCHARDISPMODE_2: in std_logic := 'U';
		TXCHARDISPMODE_3: in std_logic := 'U';
		TXCHARDISPVAL_0: in std_logic := 'U';
		TXCHARDISPVAL_1: in std_logic := 'U';
		TXCHARDISPVAL_2: in std_logic := 'U';
		TXCHARDISPVAL_3: in std_logic := 'U';
		TXCHARISK_0: in std_logic := 'U';
		TXCHARISK_1: in std_logic := 'U';
		TXCHARISK_2: in std_logic := 'U';
		TXCHARISK_3: in std_logic := 'U';
		TXBYPASS8B10B_0: in std_logic := 'U';
		TXBYPASS8B10B_1: in std_logic := 'U';
		TXBYPASS8B10B_2: in std_logic := 'U';
		TXBYPASS8B10B_3: in std_logic := 'U';
		TXFORCECRCERR: in std_logic := 'U';
		TXPOLARITY: in std_logic := 'U';
		TXINHIBIT: in std_logic := 'U';
		ENCHANSYNC: in std_logic := 'U';
		ENPCOMMAALIGN: in std_logic := 'U';
		ENMCOMMAALIGN: in std_logic := 'U';
		RXPOLARITY: in std_logic := 'U';
		CHBONDI_0: in std_logic := 'U';
		CHBONDI_1: in std_logic := 'U';
		CHBONDI_2: in std_logic := 'U';
		CHBONDI_3: in std_logic := 'U';
		CONFIGIN: in std_logic := 'U';
		CONFIGENABLE: in std_logic := 'U';
		RXRECCLK: out std_logic;
		TXBUFERR: out std_logic;
		TXRUNDISP_0: out std_logic;
		TXRUNDISP_1: out std_logic;
		TXRUNDISP_2: out std_logic;
		TXRUNDISP_3: out std_logic;
		TXKERR_0: out std_logic;
		TXKERR_1: out std_logic;
		TXKERR_2: out std_logic;
		TXKERR_3: out std_logic;
		RXREALIGN: out std_logic;
		RXCOMMADET: out std_logic;
		RXLOSSOFSYNC_0: out std_logic;
		RXLOSSOFSYNC_1: out std_logic;
		RXCLKCORCNT_0: out std_logic;
		RXCLKCORCNT_1: out std_logic;
		RXCLKCORCNT_2: out std_logic;
		RXDATA_0: out std_logic;
		RXDATA_1: out std_logic;
		RXDATA_2: out std_logic;
		RXDATA_3: out std_logic;
		RXDATA_4: out std_logic;
		RXDATA_5: out std_logic;
		RXDATA_6: out std_logic;
		RXDATA_7: out std_logic;
		RXDATA_8: out std_logic;
		RXDATA_9: out std_logic;
		RXDATA_10: out std_logic;
		RXDATA_11: out std_logic;
		RXDATA_12: out std_logic;
		RXDATA_13: out std_logic;
		RXDATA_14: out std_logic;
		RXDATA_15: out std_logic;
		RXDATA_16: out std_logic;
		RXDATA_17: out std_logic;
		RXDATA_18: out std_logic;
		RXDATA_19: out std_logic;
		RXDATA_20: out std_logic;
		RXDATA_21: out std_logic;
		RXDATA_22: out std_logic;
		RXDATA_23: out std_logic;
		RXDATA_24: out std_logic;
		RXDATA_25: out std_logic;
		RXDATA_26: out std_logic;
		RXDATA_27: out std_logic;
		RXDATA_28: out std_logic;
		RXDATA_29: out std_logic;
		RXDATA_30: out std_logic;
		RXDATA_31: out std_logic;
		RXCHARISCOMMA_0: out std_logic;
		RXCHARISCOMMA_1: out std_logic;
		RXCHARISCOMMA_2: out std_logic;
		RXCHARISCOMMA_3: out std_logic;
		RXCHARISK_0: out std_logic;
		RXCHARISK_1: out std_logic;
		RXCHARISK_2: out std_logic;
		RXCHARISK_3: out std_logic;
		RXNOTINTABLE_0: out std_logic;
		RXNOTINTABLE_1: out std_logic;
		RXNOTINTABLE_2: out std_logic;
		RXNOTINTABLE_3: out std_logic;
		RXDISPERR_0: out std_logic;
		RXDISPERR_1: out std_logic;
		RXDISPERR_2: out std_logic;
		RXDISPERR_3: out std_logic;
		RXRUNDISP_0: out std_logic;
		RXRUNDISP_1: out std_logic;
		RXRUNDISP_2: out std_logic;
		RXRUNDISP_3: out std_logic;
		RXBUFSTATUS_0: out std_logic;
		RXBUFSTATUS_1: out std_logic;
		RXCHECKINGCRC: out std_logic;
		RXCRCERR: out std_logic;
		CHBONDO_0: out std_logic;
		CHBONDO_1: out std_logic;
		CHBONDO_2: out std_logic;
		CHBONDO_3: out std_logic;
		CHBONDDONE: out std_logic;
		CONFIGOUT: out std_logic;
		TX_PREEMPHASIS_0: in std_logic := 'U';
		TX_PREEMPHASIS_1: in std_logic := 'U';
		TX_DIFF_CTRL_0: in std_logic := 'U';
		TX_DIFF_CTRL_1: in std_logic := 'U';
		TX_DIFF_CTRL_2: in std_logic := 'U';
		TERMINATION_IMP: in std_logic := 'U';
		SERDES_10B: in std_logic := 'U';
		ALIGN_COMMA_MSB: in std_logic := 'U';
		PCOMMA_DETECT: in std_logic := 'U';
		MCOMMA_DETECT: in std_logic := 'U';
		PCOMMA_10B_VALUE_9: in std_logic := 'U';
		PCOMMA_10B_VALUE_8: in std_logic := 'U';
		PCOMMA_10B_VALUE_7: in std_logic := 'U';
		PCOMMA_10B_VALUE_6: in std_logic := 'U';
		PCOMMA_10B_VALUE_5: in std_logic := 'U';
		PCOMMA_10B_VALUE_4: in std_logic := 'U';
		PCOMMA_10B_VALUE_3: in std_logic := 'U';
		PCOMMA_10B_VALUE_2: in std_logic := 'U';
		PCOMMA_10B_VALUE_1: in std_logic := 'U';
		PCOMMA_10B_VALUE_0: in std_logic := 'U';
		MCOMMA_10B_VALUE_9: in std_logic := 'U';
		MCOMMA_10B_VALUE_8: in std_logic := 'U';
		MCOMMA_10B_VALUE_7: in std_logic := 'U';
		MCOMMA_10B_VALUE_6: in std_logic := 'U';
		MCOMMA_10B_VALUE_5: in std_logic := 'U';
		MCOMMA_10B_VALUE_4: in std_logic := 'U';
		MCOMMA_10B_VALUE_3: in std_logic := 'U';
		MCOMMA_10B_VALUE_2: in std_logic := 'U';
		MCOMMA_10B_VALUE_1: in std_logic := 'U';
		MCOMMA_10B_VALUE_0: in std_logic := 'U';
		COMMA_10B_MASK_9: in std_logic := 'U';
		COMMA_10B_MASK_8: in std_logic := 'U';
		COMMA_10B_MASK_7: in std_logic := 'U';
		COMMA_10B_MASK_6: in std_logic := 'U';
		COMMA_10B_MASK_5: in std_logic := 'U';
		COMMA_10B_MASK_4: in std_logic := 'U';
		COMMA_10B_MASK_3: in std_logic := 'U';
		COMMA_10B_MASK_2: in std_logic := 'U';
		COMMA_10B_MASK_1: in std_logic := 'U';
		COMMA_10B_MASK_0: in std_logic := 'U';
		DEC_PCOMMA_DETECT: in std_logic := 'U';
		DEC_MCOMMA_DETECT: in std_logic := 'U';
		DEC_VALID_COMMA_ONLY: in std_logic := 'U';
		RX_LOSS_OF_SYNC_FSM: in std_logic := 'U';
		RX_LOS_INVALID_INCR_0: in std_logic := 'U';
		RX_LOS_INVALID_INCR_1: in std_logic := 'U';
		RX_LOS_INVALID_INCR_2: in std_logic := 'U';
		RX_LOS_THRESHOLD_0: in std_logic := 'U';
		RX_LOS_THRESHOLD_1: in std_logic := 'U';
		RX_LOS_THRESHOLD_2: in std_logic := 'U';
		RX_DECODE_USE: in std_logic := 'U';
		RX_BUFFER_USE: in std_logic := 'U';
		TX_BUFFER_USE: in std_logic := 'U';
		CLK_CORRECT_USE: in std_logic := 'U';
		CLK_COR_SEQ_LEN_0: in std_logic := 'U';
		CLK_COR_SEQ_LEN_1: in std_logic := 'U';
		CLK_COR_KEEP_IDLE: in std_logic := 'U';
		CLK_COR_REPEAT_WAIT_0: in std_logic := 'U';
		CLK_COR_REPEAT_WAIT_1: in std_logic := 'U';
		CLK_COR_REPEAT_WAIT_2: in std_logic := 'U';
		CLK_COR_REPEAT_WAIT_3: in std_logic := 'U';
		CLK_COR_REPEAT_WAIT_4: in std_logic := 'U';
		CLK_COR_INSERT_IDLE_FLAG: in std_logic := 'U';
		CLK_COR_SEQ_1_1_0: in std_logic := 'U';
		CLK_COR_SEQ_1_1_1: in std_logic := 'U';
		CLK_COR_SEQ_1_1_2: in std_logic := 'U';
		CLK_COR_SEQ_1_1_3: in std_logic := 'U';
		CLK_COR_SEQ_1_1_4: in std_logic := 'U';
		CLK_COR_SEQ_1_1_5: in std_logic := 'U';
		CLK_COR_SEQ_1_1_6: in std_logic := 'U';
		CLK_COR_SEQ_1_1_7: in std_logic := 'U';
		CLK_COR_SEQ_1_1_8: in std_logic := 'U';
		CLK_COR_SEQ_1_1_9: in std_logic := 'U';
		CLK_COR_SEQ_1_1_10: in std_logic := 'U';
		CLK_COR_SEQ_1_2_0: in std_logic := 'U';
		CLK_COR_SEQ_1_2_1: in std_logic := 'U';
		CLK_COR_SEQ_1_2_2: in std_logic := 'U';
		CLK_COR_SEQ_1_2_3: in std_logic := 'U';
		CLK_COR_SEQ_1_2_4: in std_logic := 'U';
		CLK_COR_SEQ_1_2_5: in std_logic := 'U';
		CLK_COR_SEQ_1_2_6: in std_logic := 'U';
		CLK_COR_SEQ_1_2_7: in std_logic := 'U';
		CLK_COR_SEQ_1_2_8: in std_logic := 'U';
		CLK_COR_SEQ_1_2_9: in std_logic := 'U';
		CLK_COR_SEQ_1_2_10: in std_logic := 'U';
		CLK_COR_SEQ_1_3_0: in std_logic := 'U';
		CLK_COR_SEQ_1_3_1: in std_logic := 'U';
		CLK_COR_SEQ_1_3_2: in std_logic := 'U';
		CLK_COR_SEQ_1_3_3: in std_logic := 'U';
		CLK_COR_SEQ_1_3_4: in std_logic := 'U';
		CLK_COR_SEQ_1_3_5: in std_logic := 'U';
		CLK_COR_SEQ_1_3_6: in std_logic := 'U';
		CLK_COR_SEQ_1_3_7: in std_logic := 'U';
		CLK_COR_SEQ_1_3_8: in std_logic := 'U';
		CLK_COR_SEQ_1_3_9: in std_logic := 'U';
		CLK_COR_SEQ_1_3_10: in std_logic := 'U';
		CLK_COR_SEQ_1_4_0: in std_logic := 'U';
		CLK_COR_SEQ_1_4_1: in std_logic := 'U';
		CLK_COR_SEQ_1_4_2: in std_logic := 'U';
		CLK_COR_SEQ_1_4_3: in std_logic := 'U';
		CLK_COR_SEQ_1_4_4: in std_logic := 'U';
		CLK_COR_SEQ_1_4_5: in std_logic := 'U';
		CLK_COR_SEQ_1_4_6: in std_logic := 'U';
		CLK_COR_SEQ_1_4_7: in std_logic := 'U';
		CLK_COR_SEQ_1_4_8: in std_logic := 'U';
		CLK_COR_SEQ_1_4_9: in std_logic := 'U';
		CLK_COR_SEQ_1_4_10: in std_logic := 'U';
		CLK_COR_SEQ_2_USE: in std_logic := 'U';
		CLK_COR_SEQ_2_1_0: in std_logic := 'U';
		CLK_COR_SEQ_2_1_1: in std_logic := 'U';
		CLK_COR_SEQ_2_1_2: in std_logic := 'U';
		CLK_COR_SEQ_2_1_3: in std_logic := 'U';
		CLK_COR_SEQ_2_1_4: in std_logic := 'U';
		CLK_COR_SEQ_2_1_5: in std_logic := 'U';
		CLK_COR_SEQ_2_1_6: in std_logic := 'U';
		CLK_COR_SEQ_2_1_7: in std_logic := 'U';
		CLK_COR_SEQ_2_1_8: in std_logic := 'U';
		CLK_COR_SEQ_2_1_9: in std_logic := 'U';
		CLK_COR_SEQ_2_1_10: in std_logic := 'U';
		CLK_COR_SEQ_2_2_0: in std_logic := 'U';
		CLK_COR_SEQ_2_2_1: in std_logic := 'U';
		CLK_COR_SEQ_2_2_2: in std_logic := 'U';
		CLK_COR_SEQ_2_2_3: in std_logic := 'U';
		CLK_COR_SEQ_2_2_4: in std_logic := 'U';
		CLK_COR_SEQ_2_2_5: in std_logic := 'U';
		CLK_COR_SEQ_2_2_6: in std_logic := 'U';
		CLK_COR_SEQ_2_2_7: in std_logic := 'U';
		CLK_COR_SEQ_2_2_8: in std_logic := 'U';
		CLK_COR_SEQ_2_2_9: in std_logic := 'U';
		CLK_COR_SEQ_2_2_10: in std_logic := 'U';
		CLK_COR_SEQ_2_3_0: in std_logic := 'U';
		CLK_COR_SEQ_2_3_1: in std_logic := 'U';
		CLK_COR_SEQ_2_3_2: in std_logic := 'U';
		CLK_COR_SEQ_2_3_3: in std_logic := 'U';
		CLK_COR_SEQ_2_3_4: in std_logic := 'U';
		CLK_COR_SEQ_2_3_5: in std_logic := 'U';
		CLK_COR_SEQ_2_3_6: in std_logic := 'U';
		CLK_COR_SEQ_2_3_7: in std_logic := 'U';
		CLK_COR_SEQ_2_3_8: in std_logic := 'U';
		CLK_COR_SEQ_2_3_9: in std_logic := 'U';
		CLK_COR_SEQ_2_3_10: in std_logic := 'U';
		CLK_COR_SEQ_2_4_0: in std_logic := 'U';
		CLK_COR_SEQ_2_4_1: in std_logic := 'U';
		CLK_COR_SEQ_2_4_2: in std_logic := 'U';
		CLK_COR_SEQ_2_4_3: in std_logic := 'U';
		CLK_COR_SEQ_2_4_4: in std_logic := 'U';
		CLK_COR_SEQ_2_4_5: in std_logic := 'U';
		CLK_COR_SEQ_2_4_6: in std_logic := 'U';
		CLK_COR_SEQ_2_4_7: in std_logic := 'U';
		CLK_COR_SEQ_2_4_8: in std_logic := 'U';
		CLK_COR_SEQ_2_4_9: in std_logic := 'U';
		CLK_COR_SEQ_2_4_10: in std_logic := 'U';
		CHAN_BOND_MODE_0: in std_logic := 'U';
		CHAN_BOND_MODE_1: in std_logic := 'U';
		CHAN_BOND_SEQ_LEN_0: in std_logic := 'U';
		CHAN_BOND_SEQ_LEN_1: in std_logic := 'U';
		CHAN_BOND_SEQ_1_1_0: in std_logic := 'U';
		CHAN_BOND_SEQ_1_1_1: in std_logic := 'U';
		CHAN_BOND_SEQ_1_1_2: in std_logic := 'U';
		CHAN_BOND_SEQ_1_1_3: in std_logic := 'U';
		CHAN_BOND_SEQ_1_1_4: in std_logic := 'U';
		CHAN_BOND_SEQ_1_1_5: in std_logic := 'U';
		CHAN_BOND_SEQ_1_1_6: in std_logic := 'U';
		CHAN_BOND_SEQ_1_1_7: in std_logic := 'U';
		CHAN_BOND_SEQ_1_1_8: in std_logic := 'U';
		CHAN_BOND_SEQ_1_1_9: in std_logic := 'U';
		CHAN_BOND_SEQ_1_1_10: in std_logic := 'U';
		CHAN_BOND_SEQ_1_2_0: in std_logic := 'U';
		CHAN_BOND_SEQ_1_2_1: in std_logic := 'U';
		CHAN_BOND_SEQ_1_2_2: in std_logic := 'U';
		CHAN_BOND_SEQ_1_2_3: in std_logic := 'U';
		CHAN_BOND_SEQ_1_2_4: in std_logic := 'U';
		CHAN_BOND_SEQ_1_2_5: in std_logic := 'U';
		CHAN_BOND_SEQ_1_2_6: in std_logic := 'U';
		CHAN_BOND_SEQ_1_2_7: in std_logic := 'U';
		CHAN_BOND_SEQ_1_2_8: in std_logic := 'U';
		CHAN_BOND_SEQ_1_2_9: in std_logic := 'U';
		CHAN_BOND_SEQ_1_2_10: in std_logic := 'U';
		CHAN_BOND_SEQ_1_3_0: in std_logic := 'U';
		CHAN_BOND_SEQ_1_3_1: in std_logic := 'U';
		CHAN_BOND_SEQ_1_3_2: in std_logic := 'U';
		CHAN_BOND_SEQ_1_3_3: in std_logic := 'U';
		CHAN_BOND_SEQ_1_3_4: in std_logic := 'U';
		CHAN_BOND_SEQ_1_3_5: in std_logic := 'U';
		CHAN_BOND_SEQ_1_3_6: in std_logic := 'U';
		CHAN_BOND_SEQ_1_3_7: in std_logic := 'U';
		CHAN_BOND_SEQ_1_3_8: in std_logic := 'U';
		CHAN_BOND_SEQ_1_3_9: in std_logic := 'U';
		CHAN_BOND_SEQ_1_3_10: in std_logic := 'U';
		CHAN_BOND_SEQ_1_4_0: in std_logic := 'U';
		CHAN_BOND_SEQ_1_4_1: in std_logic := 'U';
		CHAN_BOND_SEQ_1_4_2: in std_logic := 'U';
		CHAN_BOND_SEQ_1_4_3: in std_logic := 'U';
		CHAN_BOND_SEQ_1_4_4: in std_logic := 'U';
		CHAN_BOND_SEQ_1_4_5: in std_logic := 'U';
		CHAN_BOND_SEQ_1_4_6: in std_logic := 'U';
		CHAN_BOND_SEQ_1_4_7: in std_logic := 'U';
		CHAN_BOND_SEQ_1_4_8: in std_logic := 'U';
		CHAN_BOND_SEQ_1_4_9: in std_logic := 'U';
		CHAN_BOND_SEQ_1_4_10: in std_logic := 'U';
		CHAN_BOND_SEQ_2_USE: in std_logic := 'U';
		CHAN_BOND_SEQ_2_1_0: in std_logic := 'U';
		CHAN_BOND_SEQ_2_1_1: in std_logic := 'U';
		CHAN_BOND_SEQ_2_1_2: in std_logic := 'U';
		CHAN_BOND_SEQ_2_1_3: in std_logic := 'U';
		CHAN_BOND_SEQ_2_1_4: in std_logic := 'U';
		CHAN_BOND_SEQ_2_1_5: in std_logic := 'U';
		CHAN_BOND_SEQ_2_1_6: in std_logic := 'U';
		CHAN_BOND_SEQ_2_1_7: in std_logic := 'U';
		CHAN_BOND_SEQ_2_1_8: in std_logic := 'U';
		CHAN_BOND_SEQ_2_1_9: in std_logic := 'U';
		CHAN_BOND_SEQ_2_1_10: in std_logic := 'U';
		CHAN_BOND_SEQ_2_2_0: in std_logic := 'U';
		CHAN_BOND_SEQ_2_2_1: in std_logic := 'U';
		CHAN_BOND_SEQ_2_2_2: in std_logic := 'U';
		CHAN_BOND_SEQ_2_2_3: in std_logic := 'U';
		CHAN_BOND_SEQ_2_2_4: in std_logic := 'U';
		CHAN_BOND_SEQ_2_2_5: in std_logic := 'U';
		CHAN_BOND_SEQ_2_2_6: in std_logic := 'U';
		CHAN_BOND_SEQ_2_2_7: in std_logic := 'U';
		CHAN_BOND_SEQ_2_2_8: in std_logic := 'U';
		CHAN_BOND_SEQ_2_2_9: in std_logic := 'U';
		CHAN_BOND_SEQ_2_2_10: in std_logic := 'U';
		CHAN_BOND_SEQ_2_3_0: in std_logic := 'U';
		CHAN_BOND_SEQ_2_3_1: in std_logic := 'U';
		CHAN_BOND_SEQ_2_3_2: in std_logic := 'U';
		CHAN_BOND_SEQ_2_3_3: in std_logic := 'U';
		CHAN_BOND_SEQ_2_3_4: in std_logic := 'U';
		CHAN_BOND_SEQ_2_3_5: in std_logic := 'U';
		CHAN_BOND_SEQ_2_3_6: in std_logic := 'U';
		CHAN_BOND_SEQ_2_3_7: in std_logic := 'U';
		CHAN_BOND_SEQ_2_3_8: in std_logic := 'U';
		CHAN_BOND_SEQ_2_3_9: in std_logic := 'U';
		CHAN_BOND_SEQ_2_3_10: in std_logic := 'U';
		CHAN_BOND_SEQ_2_4_0: in std_logic := 'U';
		CHAN_BOND_SEQ_2_4_1: in std_logic := 'U';
		CHAN_BOND_SEQ_2_4_2: in std_logic := 'U';
		CHAN_BOND_SEQ_2_4_3: in std_logic := 'U';
		CHAN_BOND_SEQ_2_4_4: in std_logic := 'U';
		CHAN_BOND_SEQ_2_4_5: in std_logic := 'U';
		CHAN_BOND_SEQ_2_4_6: in std_logic := 'U';
		CHAN_BOND_SEQ_2_4_7: in std_logic := 'U';
		CHAN_BOND_SEQ_2_4_8: in std_logic := 'U';
		CHAN_BOND_SEQ_2_4_9: in std_logic := 'U';
		CHAN_BOND_SEQ_2_4_10: in std_logic := 'U';
		CHAN_BOND_WAIT_0: in std_logic := 'U';
		CHAN_BOND_WAIT_1: in std_logic := 'U';
		CHAN_BOND_WAIT_2: in std_logic := 'U';
		CHAN_BOND_WAIT_3: in std_logic := 'U';
		CHAN_BOND_OFFSET_0: in std_logic := 'U';
		CHAN_BOND_OFFSET_1: in std_logic := 'U';
		CHAN_BOND_OFFSET_2: in std_logic := 'U';
		CHAN_BOND_OFFSET_3: in std_logic := 'U';
		CHAN_BOND_LIMIT_0: in std_logic := 'U';
		CHAN_BOND_LIMIT_1: in std_logic := 'U';
		CHAN_BOND_LIMIT_2: in std_logic := 'U';
		CHAN_BOND_LIMIT_3: in std_logic := 'U';
		CHAN_BOND_LIMIT_4: in std_logic := 'U';
		CHAN_BOND_ONE_SHOT: in std_logic := 'U';
		CRC_FORMAT_0: in std_logic := 'U';
		CRC_FORMAT_1: in std_logic := 'U';
		CRC_START_OF_PKT_0: in std_logic := 'U';
		CRC_START_OF_PKT_1: in std_logic := 'U';
		CRC_START_OF_PKT_2: in std_logic := 'U';
		CRC_START_OF_PKT_3: in std_logic := 'U';
		CRC_START_OF_PKT_4: in std_logic := 'U';
		CRC_START_OF_PKT_5: in std_logic := 'U';
		CRC_START_OF_PKT_6: in std_logic := 'U';
		CRC_START_OF_PKT_7: in std_logic := 'U';
		CRC_END_OF_PKT_0: in std_logic := 'U';
		CRC_END_OF_PKT_1: in std_logic := 'U';
		CRC_END_OF_PKT_2: in std_logic := 'U';
		CRC_END_OF_PKT_3: in std_logic := 'U';
		CRC_END_OF_PKT_4: in std_logic := 'U';
		CRC_END_OF_PKT_5: in std_logic := 'U';
		CRC_END_OF_PKT_6: in std_logic := 'U';
		CRC_END_OF_PKT_7: in std_logic := 'U';
		RX_CRC_USE: in std_logic := 'U';
		TX_CRC_USE: in std_logic := 'U';
		TX_CRC_FORCE_VALUE_0: in std_logic := 'U';
		TX_CRC_FORCE_VALUE_1: in std_logic := 'U';
		TX_CRC_FORCE_VALUE_2: in std_logic := 'U';
		TX_CRC_FORCE_VALUE_3: in std_logic := 'U';
		TX_CRC_FORCE_VALUE_4: in std_logic := 'U';
		TX_CRC_FORCE_VALUE_5: in std_logic := 'U';
		TX_CRC_FORCE_VALUE_6: in std_logic := 'U';
		TX_CRC_FORCE_VALUE_7: in std_logic := 'U';
		RX_DATA_WIDTH_0: in std_logic := 'U';
		RX_DATA_WIDTH_1: in std_logic := 'U';
		TX_DATA_WIDTH_0: in std_logic := 'U';
		TX_DATA_WIDTH_1: in std_logic := 'U';
		REF_CLK_V_SEL: in std_logic := 'U';
		GSR: in std_logic := 'U'
	);
end gt_swift;



architecture SmartModel of gt_swift is
	attribute foreign of SmartModel : architecture is "SWIFT gt_swift";
begin
end;

----------------------------------------------------
--  
--  Library Name :  unisim
--  Unit    Name :  GT_SWIFT_BUS
--  Unit    Type :  Text Unit
--  
------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;

entity GT_SWIFT_BUS is
	port (
		TX_CRC_FORCE_VALUE : in std_logic_vector(7 downto 0);
		RXLOSSOFSYNC : out std_logic_vector(1 downto 0);
		RXCLKCORCNT : out std_logic_vector(2 downto 0);
		RXP : in std_ulogic;
		RXN : in std_ulogic;
		GSR : in std_ulogic;
		TXP : out std_ulogic;
		TXN : out std_ulogic;
		CONFIGENABLE : in std_ulogic;
		CONFIGIN : in std_ulogic;
		CONFIGOUT : out std_ulogic;
		ENMCOMMAALIGN : in std_ulogic;
		ENPCOMMAALIGN : in std_ulogic;
		CRC_END_OF_PKT : in std_logic_vector(7 downto 0);
		CRC_FORMAT : in std_logic_vector(1 downto 0);
		CRC_START_OF_PKT : in std_logic_vector(7 downto 0);
		CHAN_BOND_LIMIT : in std_logic_vector(4 downto 0);
		REFCLK : in std_ulogic;
		REFCLK2 : in std_ulogic;
		REFCLKSEL : in std_ulogic;
		RXUSRCLK : in std_ulogic;
		TXUSRCLK : in std_ulogic;
		RXUSRCLK2 : in std_ulogic;
		TXUSRCLK2 : in std_ulogic;
		RXRESET : in std_ulogic;
		TXRESET : in std_ulogic;
		POWERDOWN : in std_ulogic;
		LOOPBACK : in std_logic_vector(1 downto 0);
		TXDATA : in std_logic_vector(31 downto 0);
		RX_LOSS_OF_SYNC_FSM : in std_ulogic;
		RX_LOS_INVALID_INCR : in std_logic_vector(2 downto 0);
		RX_LOS_THRESHOLD : in std_logic_vector(2 downto 0);
		TXCHARDISPMODE : in std_logic_vector(3 downto 0);
		TXCHARDISPVAL : in std_logic_vector(3 downto 0);
		TXCHARISK : in std_logic_vector(3 downto 0);
		TXBYPASS8B10B : in std_logic_vector(3 downto 0);
		TXPOLARITY : in std_ulogic;
		TXINHIBIT : in std_ulogic;
		ENCHANSYNC : in std_ulogic;
		RXPOLARITY : in std_ulogic;
		CHBONDI : in std_logic_vector(3 downto 0);
		RXRECCLK : out std_ulogic;
		TXBUFERR : out std_ulogic;
		TXFORCECRCERR : in std_ulogic;
		TXRUNDISP : out std_logic_vector(3 downto 0);
		TXKERR : out std_logic_vector(3 downto 0);
		RXREALIGN : out std_ulogic;
		RXCOMMADET : out std_ulogic;
		RXCHECKINGCRC : out std_ulogic;
		RXCRCERR : out std_ulogic;
		RXDATA : out std_logic_vector(31 downto 0);
		RXCHARISCOMMA : out std_logic_vector(3 downto 0);
		RXCHARISK : out std_logic_vector(3 downto 0);
		RXNOTINTABLE : out std_logic_vector(3 downto 0);
		RXDISPERR : out std_logic_vector(3 downto 0);
		RXRUNDISP : out std_logic_vector(3 downto 0);
		RXBUFSTATUS : out std_logic_vector(1 downto 0);
		CHBONDO : out std_logic_vector(3 downto 0);
		CHBONDDONE : out std_ulogic;
		TX_PREEMPHASIS : in std_logic_vector(1 downto 0);
		TX_DIFF_CTRL : in std_logic_vector(2 downto 0);
		TERMINATION_IMP : in std_ulogic;
		SERDES_10B : in std_ulogic;
		ALIGN_COMMA_MSB : in std_ulogic;
		PCOMMA_DETECT : in std_ulogic;
		MCOMMA_DETECT : in std_ulogic;
		PCOMMA_10B_VALUE : in std_logic_vector(0 to 9);
		MCOMMA_10B_VALUE : in std_logic_vector(0 to 9);
		COMMA_10B_MASK : in std_logic_vector(0 to 9);
		DEC_PCOMMA_DETECT : in std_ulogic;
		DEC_MCOMMA_DETECT : in std_ulogic;
		DEC_VALID_COMMA_ONLY : in std_ulogic;
		RX_DECODE_USE : in std_ulogic;
		RX_BUFFER_USE : in std_ulogic;
		TX_BUFFER_USE : in std_ulogic;
		CLK_CORRECT_USE : in std_ulogic;
		CLK_COR_SEQ_LEN : in std_logic_vector(1 downto 0);
		CLK_COR_INSERT_IDLE_FLAG : in std_ulogic;
		CLK_COR_KEEP_IDLE : in std_ulogic;
		CLK_COR_REPEAT_WAIT : in std_logic_vector(4 downto 0);
		CLK_COR_SEQ_1_1 : in std_logic_vector(10 downto 0);
		CLK_COR_SEQ_1_2 : in std_logic_vector(10 downto 0);
		CLK_COR_SEQ_1_3 : in std_logic_vector(10 downto 0);
		CLK_COR_SEQ_1_4 : in std_logic_vector(10 downto 0);
		CLK_COR_SEQ_2_USE : in std_ulogic;
		CLK_COR_SEQ_2_1 : in std_logic_vector(10 downto 0);
		CLK_COR_SEQ_2_2 : in std_logic_vector(10 downto 0);
		CLK_COR_SEQ_2_3 : in std_logic_vector(10 downto 0);
		CLK_COR_SEQ_2_4 : in std_logic_vector(10 downto 0);
		CHAN_BOND_MODE : in std_logic_vector(1 downto 0);
		CHAN_BOND_SEQ_LEN : in std_logic_vector(1 downto 0);
		CHAN_BOND_SEQ_1_1 : in std_logic_vector(10 downto 0);
		CHAN_BOND_SEQ_1_2 : in std_logic_vector(10 downto 0);
		CHAN_BOND_SEQ_1_3 : in std_logic_vector(10 downto 0);
		CHAN_BOND_SEQ_1_4 : in std_logic_vector(10 downto 0);
		CHAN_BOND_SEQ_2_USE : in std_ulogic;
		CHAN_BOND_SEQ_2_1 : in std_logic_vector(10 downto 0);
		CHAN_BOND_SEQ_2_2 : in std_logic_vector(10 downto 0);
		CHAN_BOND_SEQ_2_3 : in std_logic_vector(10 downto 0);
		CHAN_BOND_SEQ_2_4 : in std_logic_vector(10 downto 0);
		CHAN_BOND_WAIT : in std_logic_vector(3 downto 0);
		CHAN_BOND_OFFSET : in std_logic_vector(3 downto 0);
		TX_CRC_USE : in std_ulogic;
		RX_CRC_USE : in std_ulogic;
		CHAN_BOND_ONE_SHOT : in std_ulogic;
		RX_DATA_WIDTH : in std_logic_vector(1 downto 0);
		TX_DATA_WIDTH : in std_logic_vector(1 downto 0);
		BREFCLK : in std_ulogic;
		BREFCLK2 : in std_ulogic;
		REF_CLK_V_SEL : in std_ulogic
	);
end GT_SWIFT_BUS;



architecture GT_SWIFT_BUS_v of GT_SWIFT_BUS is
Component GT_SWIFT -----
	generic (
		TimingVersion : STRING := "gt_swift";
		DelayRange : STRING := "MAX";
		MC_Reference : STRING := "0000");
	port (
		TX_CRC_FORCE_VALUE : in std_logic_vector(7 downto 0);
		RXLOSSOFSYNC : out std_logic_vector(1 downto 0);
		RXCLKCORCNT : out std_logic_vector(2 downto 0);
		RXP : in std_ulogic;
		RXN : in std_ulogic;
		GSR : in std_ulogic;
		TXP : out std_ulogic;
		TXN : out std_ulogic;
		CONFIGENABLE : in std_ulogic;
		CONFIGIN : in std_ulogic;
		CONFIGOUT : out std_ulogic;
		ENMCOMMAALIGN : in std_ulogic;
		ENPCOMMAALIGN : in std_ulogic;
		CRC_END_OF_PKT : in std_logic_vector(7 downto 0);
		CRC_FORMAT : in std_logic_vector(1 downto 0);
		CRC_START_OF_PKT : in std_logic_vector(7 downto 0);
		CHAN_BOND_LIMIT : in std_logic_vector(4 downto 0);
		REFCLK : in std_ulogic;
		REFCLK2 : in std_ulogic;
		REFCLKSEL : in std_ulogic;
		RXUSRCLK : in std_ulogic;
		TXUSRCLK : in std_ulogic;
		RXUSRCLK2 : in std_ulogic;
		TXUSRCLK2 : in std_ulogic;
		RXRESET : in std_ulogic;
		TXRESET : in std_ulogic;
		POWERDOWN : in std_ulogic;
		LOOPBACK : in std_logic_vector(1 downto 0);
		TXDATA : in std_logic_vector(31 downto 0);
		RX_LOSS_OF_SYNC_FSM : in std_ulogic;
		RX_LOS_INVALID_INCR : in std_logic_vector(2 downto 0);
		RX_LOS_THRESHOLD : in std_logic_vector(2 downto 0);
		TXCHARDISPMODE : in std_logic_vector(3 downto 0);
		TXCHARDISPVAL : in std_logic_vector(3 downto 0);
		TXCHARISK : in std_logic_vector(3 downto 0);
		TXBYPASS8B10B : in std_logic_vector(3 downto 0);
		TXPOLARITY : in std_ulogic;
		TXINHIBIT : in std_ulogic;
		ENCHANSYNC : in std_ulogic;
		RXPOLARITY : in std_ulogic;
		CHBONDI : in std_logic_vector(3 downto 0);
		RXRECCLK : out std_ulogic;
		TXBUFERR : out std_ulogic;
		TXFORCECRCERR : in std_ulogic;
		TXRUNDISP : out std_logic_vector(3 downto 0);
		TXKERR : out std_logic_vector(3 downto 0);
		RXREALIGN : out std_ulogic;
		RXCOMMADET : out std_ulogic;
		RXCHECKINGCRC : out std_ulogic;
		RXCRCERR : out std_ulogic;
		RXDATA : out std_logic_vector(31 downto 0);
		RXCHARISCOMMA : out std_logic_vector(3 downto 0);
		RXCHARISK : out std_logic_vector(3 downto 0);
		RXNOTINTABLE : out std_logic_vector(3 downto 0);
		RXDISPERR : out std_logic_vector(3 downto 0);
		RXRUNDISP : out std_logic_vector(3 downto 0);
		RXBUFSTATUS : out std_logic_vector(1 downto 0);
		CHBONDO : out std_logic_vector(3 downto 0);
		CHBONDDONE : out std_ulogic;
		TX_PREEMPHASIS : in std_logic_vector(1 downto 0);
		TX_DIFF_CTRL : in std_logic_vector(2 downto 0);
		TERMINATION_IMP : in std_ulogic;
		SERDES_10B : in std_ulogic;
		ALIGN_COMMA_MSB : in std_ulogic;
		PCOMMA_DETECT : in std_ulogic;
		MCOMMA_DETECT : in std_ulogic;
		PCOMMA_10B_VALUE : in std_logic_vector(0 to 9);
		MCOMMA_10B_VALUE : in std_logic_vector(0 to 9);
		COMMA_10B_MASK : in std_logic_vector(0 to 9);
		DEC_PCOMMA_DETECT : in std_ulogic;
		DEC_MCOMMA_DETECT : in std_ulogic;
		DEC_VALID_COMMA_ONLY : in std_ulogic;
		RX_DECODE_USE : in std_ulogic;
		RX_BUFFER_USE : in std_ulogic;
		TX_BUFFER_USE : in std_ulogic;
		CLK_CORRECT_USE : in std_ulogic;
		CLK_COR_SEQ_LEN : in std_logic_vector(1 downto 0);
		CLK_COR_INSERT_IDLE_FLAG : in std_ulogic;
		CLK_COR_KEEP_IDLE : in std_ulogic;
		CLK_COR_REPEAT_WAIT : in std_logic_vector(4 downto 0);
		CLK_COR_SEQ_1_1 : in std_logic_vector(10 downto 0);
		CLK_COR_SEQ_1_2 : in std_logic_vector(10 downto 0);
		CLK_COR_SEQ_1_3 : in std_logic_vector(10 downto 0);
		CLK_COR_SEQ_1_4 : in std_logic_vector(10 downto 0);
		CLK_COR_SEQ_2_USE : in std_ulogic;
		CLK_COR_SEQ_2_1 : in std_logic_vector(10 downto 0);
		CLK_COR_SEQ_2_2 : in std_logic_vector(10 downto 0);
		CLK_COR_SEQ_2_3 : in std_logic_vector(10 downto 0);
		CLK_COR_SEQ_2_4 : in std_logic_vector(10 downto 0);
		CHAN_BOND_MODE : in std_logic_vector(1 downto 0);
		CHAN_BOND_SEQ_LEN : in std_logic_vector(1 downto 0);
		CHAN_BOND_SEQ_1_1 : in std_logic_vector(10 downto 0);
		CHAN_BOND_SEQ_1_2 : in std_logic_vector(10 downto 0);
		CHAN_BOND_SEQ_1_3 : in std_logic_vector(10 downto 0);
		CHAN_BOND_SEQ_1_4 : in std_logic_vector(10 downto 0);
		CHAN_BOND_SEQ_2_USE : in std_ulogic;
		CHAN_BOND_SEQ_2_1 : in std_logic_vector(10 downto 0);
		CHAN_BOND_SEQ_2_2 : in std_logic_vector(10 downto 0);
		CHAN_BOND_SEQ_2_3 : in std_logic_vector(10 downto 0);
		CHAN_BOND_SEQ_2_4 : in std_logic_vector(10 downto 0);
		CHAN_BOND_WAIT : in std_logic_vector(3 downto 0);
		CHAN_BOND_OFFSET : in std_logic_vector(3 downto 0);
		TX_CRC_USE : in std_ulogic;
		RX_CRC_USE : in std_ulogic;
		CHAN_BOND_ONE_SHOT : in std_ulogic;
		RX_DATA_WIDTH : in std_logic_vector(1 downto 0);
		TX_DATA_WIDTH : in std_logic_vector(1 downto 0);
		BREFCLK : in std_ulogic;
		BREFCLK2 : in std_ulogic;
		REF_CLK_V_SEL : in std_ulogic
);
end component;

for all : GT_SWIFT
use entity work.GT_SWIFT
	port map (
		TXFORCECRCERR => TXFORCECRCERR,
		RX_CRC_USE => RX_CRC_USE,
		TX_CRC_USE => TX_CRC_USE,
		CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT,
		CONFIGENABLE => CONFIGENABLE,
		CONFIGIN => CONFIGIN,
		CONFIGOUT => CONFIGOUT,
		ENMCOMMAALIGN => ENMCOMMAALIGN,
		ENPCOMMAALIGN => ENPCOMMAALIGN,
		TX_CRC_FORCE_VALUE_0 => TX_CRC_FORCE_VALUE(0),
		TX_CRC_FORCE_VALUE_1 => TX_CRC_FORCE_VALUE(1),
		TX_CRC_FORCE_VALUE_2 => TX_CRC_FORCE_VALUE(2),
		TX_CRC_FORCE_VALUE_3 => TX_CRC_FORCE_VALUE(3),
		TX_CRC_FORCE_VALUE_4 => TX_CRC_FORCE_VALUE(4),
		TX_CRC_FORCE_VALUE_5 => TX_CRC_FORCE_VALUE(5),
		TX_CRC_FORCE_VALUE_6 => TX_CRC_FORCE_VALUE(6),
		TX_CRC_FORCE_VALUE_7 => TX_CRC_FORCE_VALUE(7),
		CRC_END_OF_PKT_0 => CRC_END_OF_PKT(0),
		CRC_END_OF_PKT_1 => CRC_END_OF_PKT(1),
		CRC_END_OF_PKT_2 => CRC_END_OF_PKT(2),
		CRC_END_OF_PKT_3 => CRC_END_OF_PKT(3),
		CRC_END_OF_PKT_4 => CRC_END_OF_PKT(4),
		CRC_END_OF_PKT_5 => CRC_END_OF_PKT(5),
		CRC_END_OF_PKT_6 => CRC_END_OF_PKT(6),
		CRC_END_OF_PKT_7 => CRC_END_OF_PKT(7),
		CRC_FORMAT_0 => CRC_FORMAT(0),
		CRC_FORMAT_1 => CRC_FORMAT(1),
		CRC_START_OF_PKT_0 => CRC_START_OF_PKT(0),
		CRC_START_OF_PKT_1 => CRC_START_OF_PKT(1),
		CRC_START_OF_PKT_2 => CRC_START_OF_PKT(2),
		CRC_START_OF_PKT_3 => CRC_START_OF_PKT(3),
		CRC_START_OF_PKT_4 => CRC_START_OF_PKT(4),
		CRC_START_OF_PKT_5 => CRC_START_OF_PKT(5),
		CRC_START_OF_PKT_6 => CRC_START_OF_PKT(6),
		CRC_START_OF_PKT_7 => CRC_START_OF_PKT(7),
		CHAN_BOND_LIMIT_0 => CHAN_BOND_LIMIT(0),
		CHAN_BOND_LIMIT_1 => CHAN_BOND_LIMIT(1),
		CHAN_BOND_LIMIT_2 => CHAN_BOND_LIMIT(2),
		CHAN_BOND_LIMIT_3 => CHAN_BOND_LIMIT(3),
		CHAN_BOND_LIMIT_4 => CHAN_BOND_LIMIT(4),

		RXLOSSOFSYNC_0 => RXLOSSOFSYNC(0),
		RXLOSSOFSYNC_1 => RXLOSSOFSYNC(1),
		RXCLKCORCNT_0 => RXCLKCORCNT(0),
		RXCLKCORCNT_1 => RXCLKCORCNT(1),
		RXCLKCORCNT_2 => RXCLKCORCNT(2),
		RXCHECKINGCRC => RXCHECKINGCRC,
		RXCRCERR => RXCRCERR,
		RXP => RXP,
		RXN => RXN,
		TXP => TXP,
		TXN => TXN,
		GSR => GSR,
		REFCLK => REFCLK,
		REFCLK2 => REFCLK2,
		REFCLKSEL => REFCLKSEL,
		RXUSRCLK => RXUSRCLK,
		TXUSRCLK => TXUSRCLK,
		RXUSRCLK2 => RXUSRCLK2,
		TXUSRCLK2 => TXUSRCLK2,
		RXRESET => RXRESET,
		TXRESET => TXRESET,
		POWERDOWN => POWERDOWN,
		LOOPBACK_0 => LOOPBACK(0),
		LOOPBACK_1 => LOOPBACK(1),
		TXDATA_0 => TXDATA(0),
		TXDATA_1 => TXDATA(1),
		TXDATA_2 => TXDATA(2),
		TXDATA_3 => TXDATA(3),
		TXDATA_4 => TXDATA(4),
		TXDATA_5 => TXDATA(5),
		TXDATA_6 => TXDATA(6),
		TXDATA_7 => TXDATA(7),
		TXDATA_8 => TXDATA(8),
		TXDATA_9 => TXDATA(9),
		TXDATA_10 => TXDATA(10),
		TXDATA_11 => TXDATA(11),
		TXDATA_12 => TXDATA(12),
		TXDATA_13 => TXDATA(13),
		TXDATA_14 => TXDATA(14),
		TXDATA_15 => TXDATA(15),
		TXDATA_16 => TXDATA(16),
		TXDATA_17 => TXDATA(17),
		TXDATA_18 => TXDATA(18),
		TXDATA_19 => TXDATA(19),
		TXDATA_20 => TXDATA(20),
		TXDATA_21 => TXDATA(21),
		TXDATA_22 => TXDATA(22),
		TXDATA_23 => TXDATA(23),
		TXDATA_24 => TXDATA(24),
		TXDATA_25 => TXDATA(25),
		TXDATA_26 => TXDATA(26),
		TXDATA_27 => TXDATA(27),
		TXDATA_28 => TXDATA(28),
		TXDATA_29 => TXDATA(29),
		TXDATA_30 => TXDATA(30),
		TXDATA_31 => TXDATA(31),
		TXCHARDISPMODE_0 => TXCHARDISPMODE(0),
		TXCHARDISPMODE_1 => TXCHARDISPMODE(1),
		TXCHARDISPMODE_2 => TXCHARDISPMODE(2),
		TXCHARDISPMODE_3 => TXCHARDISPMODE(3),
		TXCHARDISPVAL_0 => TXCHARDISPVAL(0),
		TXCHARDISPVAL_1 => TXCHARDISPVAL(1),
		TXCHARDISPVAL_2 => TXCHARDISPVAL(2),
		TXCHARDISPVAL_3 => TXCHARDISPVAL(3),
		TXCHARISK_0 => TXCHARISK(0),
		TXCHARISK_1 => TXCHARISK(1),
		TXCHARISK_2 => TXCHARISK(2),
		TXCHARISK_3 => TXCHARISK(3),
		TXBYPASS8B10B_0 => TXBYPASS8B10B(0),
		TXBYPASS8B10B_1 => TXBYPASS8B10B(1),
		TXBYPASS8B10B_2 => TXBYPASS8B10B(2),
		TXBYPASS8B10B_3 => TXBYPASS8B10B(3),
		TXPOLARITY => TXPOLARITY,
		TXINHIBIT => TXINHIBIT,
		ENCHANSYNC => ENCHANSYNC,
		RXPOLARITY => RXPOLARITY,
		CHBONDI_0 => CHBONDI(0),
		CHBONDI_1 => CHBONDI(1),
		CHBONDI_2 => CHBONDI(2),
		CHBONDI_3 => CHBONDI(3),
		RXRECCLK => RXRECCLK,
		TXBUFERR => TXBUFERR,
		TXRUNDISP_0 => TXRUNDISP(0),
		TXRUNDISP_1 => TXRUNDISP(1),
		TXRUNDISP_2 => TXRUNDISP(2),
		TXRUNDISP_3 => TXRUNDISP(3),
		TXKERR_0 => TXKERR(0),
		TXKERR_1 => TXKERR(1),
		TXKERR_2 => TXKERR(2),
		TXKERR_3 => TXKERR(3),
		RXREALIGN => RXREALIGN,
		RXCOMMADET => RXCOMMADET,
		RXDATA_0 => RXDATA(0),
		RXDATA_1 => RXDATA(1),
		RXDATA_2 => RXDATA(2),
		RXDATA_3 => RXDATA(3),
		RXDATA_4 => RXDATA(4),
		RXDATA_5 => RXDATA(5),
		RXDATA_6 => RXDATA(6),
		RXDATA_7 => RXDATA(7),
		RXDATA_8 => RXDATA(8),
		RXDATA_9 => RXDATA(9),
		RXDATA_10 => RXDATA(10),
		RXDATA_11 => RXDATA(11),
		RXDATA_12 => RXDATA(12),
		RXDATA_13 => RXDATA(13),
		RXDATA_14 => RXDATA(14),
		RXDATA_15 => RXDATA(15),
		RXDATA_16 => RXDATA(16),
		RXDATA_17 => RXDATA(17),
		RXDATA_18 => RXDATA(18),
		RXDATA_19 => RXDATA(19),
		RXDATA_20 => RXDATA(20),
		RXDATA_21 => RXDATA(21),
		RXDATA_22 => RXDATA(22),
		RXDATA_23 => RXDATA(23),
		RXDATA_24 => RXDATA(24),
		RXDATA_25 => RXDATA(25),
		RXDATA_26 => RXDATA(26),
		RXDATA_27 => RXDATA(27),
		RXDATA_28 => RXDATA(28),
		RXDATA_29 => RXDATA(29),
		RXDATA_30 => RXDATA(30),
		RXDATA_31 => RXDATA(31),
		RXCHARISCOMMA_0 => RXCHARISCOMMA(0),
		RXCHARISCOMMA_1 => RXCHARISCOMMA(1),
		RXCHARISCOMMA_2 => RXCHARISCOMMA(2),
		RXCHARISCOMMA_3 => RXCHARISCOMMA(3),
		RXCHARISK_0 => RXCHARISK(0),
		RXCHARISK_1 => RXCHARISK(1),
		RXCHARISK_2 => RXCHARISK(2),
		RXCHARISK_3 => RXCHARISK(3),
		RXNOTINTABLE_0 => RXNOTINTABLE(0),
		RXNOTINTABLE_1 => RXNOTINTABLE(1),
		RXNOTINTABLE_2 => RXNOTINTABLE(2),
		RXNOTINTABLE_3 => RXNOTINTABLE(3),
		RXDISPERR_0 => RXDISPERR(0),
		RXDISPERR_1 => RXDISPERR(1),
		RXDISPERR_2 => RXDISPERR(2),
		RXDISPERR_3 => RXDISPERR(3),
		RXRUNDISP_0 => RXRUNDISP(0),
		RXRUNDISP_1 => RXRUNDISP(1),
		RXRUNDISP_2 => RXRUNDISP(2),
		RXRUNDISP_3 => RXRUNDISP(3),
		RXBUFSTATUS_0 => RXBUFSTATUS(0),
		RXBUFSTATUS_1 => RXBUFSTATUS(1),
		CHBONDO_0 => CHBONDO(0),
		CHBONDO_1 => CHBONDO(1),
		CHBONDO_2 => CHBONDO(2),
		CHBONDO_3 => CHBONDO(3),
		CHBONDDONE => CHBONDDONE,
		TX_PREEMPHASIS_0 => TX_PREEMPHASIS(0),
		TX_PREEMPHASIS_1 => TX_PREEMPHASIS(1),
		TX_DIFF_CTRL_0 => TX_DIFF_CTRL(0),
		TX_DIFF_CTRL_1 => TX_DIFF_CTRL(1),
		TX_DIFF_CTRL_2 => TX_DIFF_CTRL(2),
		TERMINATION_IMP => TERMINATION_IMP,
		SERDES_10B => SERDES_10B,
		ALIGN_COMMA_MSB => ALIGN_COMMA_MSB,
		PCOMMA_DETECT => PCOMMA_DETECT,
		MCOMMA_DETECT => MCOMMA_DETECT,
		PCOMMA_10B_VALUE_9 => PCOMMA_10B_VALUE(9),
		PCOMMA_10B_VALUE_8 => PCOMMA_10B_VALUE(8),
		PCOMMA_10B_VALUE_7 => PCOMMA_10B_VALUE(7),
		PCOMMA_10B_VALUE_6 => PCOMMA_10B_VALUE(6),
		PCOMMA_10B_VALUE_5 => PCOMMA_10B_VALUE(5),
		PCOMMA_10B_VALUE_4 => PCOMMA_10B_VALUE(4),
		PCOMMA_10B_VALUE_3 => PCOMMA_10B_VALUE(3),
		PCOMMA_10B_VALUE_2 => PCOMMA_10B_VALUE(2),
		PCOMMA_10B_VALUE_1 => PCOMMA_10B_VALUE(1),
		PCOMMA_10B_VALUE_0 => PCOMMA_10B_VALUE(0),
		MCOMMA_10B_VALUE_9 => MCOMMA_10B_VALUE(9),
		MCOMMA_10B_VALUE_8 => MCOMMA_10B_VALUE(8),
		MCOMMA_10B_VALUE_7 => MCOMMA_10B_VALUE(7),
		MCOMMA_10B_VALUE_6 => MCOMMA_10B_VALUE(6),
		MCOMMA_10B_VALUE_5 => MCOMMA_10B_VALUE(5),
		MCOMMA_10B_VALUE_4 => MCOMMA_10B_VALUE(4),
		MCOMMA_10B_VALUE_3 => MCOMMA_10B_VALUE(3),
		MCOMMA_10B_VALUE_2 => MCOMMA_10B_VALUE(2),
		MCOMMA_10B_VALUE_1 => MCOMMA_10B_VALUE(1),
		MCOMMA_10B_VALUE_0 => MCOMMA_10B_VALUE(0),
		COMMA_10B_MASK_9 => COMMA_10B_MASK(9),
		COMMA_10B_MASK_8 => COMMA_10B_MASK(8),
		COMMA_10B_MASK_7 => COMMA_10B_MASK(7),
		COMMA_10B_MASK_6 => COMMA_10B_MASK(6),
		COMMA_10B_MASK_5 => COMMA_10B_MASK(5),
		COMMA_10B_MASK_4 => COMMA_10B_MASK(4),
		COMMA_10B_MASK_3 => COMMA_10B_MASK(3),
		COMMA_10B_MASK_2 => COMMA_10B_MASK(2),
		COMMA_10B_MASK_1 => COMMA_10B_MASK(1),
		COMMA_10B_MASK_0 => COMMA_10B_MASK(0),
		DEC_PCOMMA_DETECT => DEC_PCOMMA_DETECT,
		DEC_MCOMMA_DETECT => DEC_MCOMMA_DETECT,
		DEC_VALID_COMMA_ONLY => DEC_VALID_COMMA_ONLY,
		RX_DECODE_USE => RX_DECODE_USE,
		RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM,
		RX_LOS_INVALID_INCR_0 => RX_LOS_INVALID_INCR(0),
		RX_LOS_INVALID_INCR_1 => RX_LOS_INVALID_INCR(1),
		RX_LOS_INVALID_INCR_2 => RX_LOS_INVALID_INCR(2),
		RX_LOS_THRESHOLD_0 => RX_LOS_THRESHOLD(0),
		RX_LOS_THRESHOLD_1 => RX_LOS_THRESHOLD(1),
		RX_LOS_THRESHOLD_2 => RX_LOS_THRESHOLD(2),
		RX_BUFFER_USE => RX_BUFFER_USE,
		TX_BUFFER_USE => TX_BUFFER_USE,
		CLK_CORRECT_USE => CLK_CORRECT_USE,
		CLK_COR_SEQ_LEN_0 => CLK_COR_SEQ_LEN(0),
		CLK_COR_SEQ_LEN_1 => CLK_COR_SEQ_LEN(1),
		CLK_COR_KEEP_IDLE => CLK_COR_KEEP_IDLE,
		CLK_COR_REPEAT_WAIT_0 => CLK_COR_REPEAT_WAIT(0),
		CLK_COR_REPEAT_WAIT_1 => CLK_COR_REPEAT_WAIT(1),
		CLK_COR_REPEAT_WAIT_2 => CLK_COR_REPEAT_WAIT(2),
		CLK_COR_REPEAT_WAIT_3 => CLK_COR_REPEAT_WAIT(3),
		CLK_COR_REPEAT_WAIT_4 => CLK_COR_REPEAT_WAIT(4),
		CLK_COR_INSERT_IDLE_FLAG => CLK_COR_INSERT_IDLE_FLAG,
		CLK_COR_SEQ_1_1_0 => CLK_COR_SEQ_1_1(0),
		CLK_COR_SEQ_1_1_1 => CLK_COR_SEQ_1_1(1),
		CLK_COR_SEQ_1_1_2 => CLK_COR_SEQ_1_1(2),
		CLK_COR_SEQ_1_1_3 => CLK_COR_SEQ_1_1(3),
		CLK_COR_SEQ_1_1_4 => CLK_COR_SEQ_1_1(4),
		CLK_COR_SEQ_1_1_5 => CLK_COR_SEQ_1_1(5),
		CLK_COR_SEQ_1_1_6 => CLK_COR_SEQ_1_1(6),
		CLK_COR_SEQ_1_1_7 => CLK_COR_SEQ_1_1(7),
		CLK_COR_SEQ_1_1_8 => CLK_COR_SEQ_1_1(8),
		CLK_COR_SEQ_1_1_9 => CLK_COR_SEQ_1_1(9),
		CLK_COR_SEQ_1_1_10 => CLK_COR_SEQ_1_1(10),
		CLK_COR_SEQ_1_2_0 => CLK_COR_SEQ_1_2(0),
		CLK_COR_SEQ_1_2_1 => CLK_COR_SEQ_1_2(1),
		CLK_COR_SEQ_1_2_2 => CLK_COR_SEQ_1_2(2),
		CLK_COR_SEQ_1_2_3 => CLK_COR_SEQ_1_2(3),
		CLK_COR_SEQ_1_2_4 => CLK_COR_SEQ_1_2(4),
		CLK_COR_SEQ_1_2_5 => CLK_COR_SEQ_1_2(5),
		CLK_COR_SEQ_1_2_6 => CLK_COR_SEQ_1_2(6),
		CLK_COR_SEQ_1_2_7 => CLK_COR_SEQ_1_2(7),
		CLK_COR_SEQ_1_2_8 => CLK_COR_SEQ_1_2(8),
		CLK_COR_SEQ_1_2_9 => CLK_COR_SEQ_1_2(9),
		CLK_COR_SEQ_1_2_10 => CLK_COR_SEQ_1_2(10),
		CLK_COR_SEQ_1_3_0 => CLK_COR_SEQ_1_3(0),
		CLK_COR_SEQ_1_3_1 => CLK_COR_SEQ_1_3(1),
		CLK_COR_SEQ_1_3_2 => CLK_COR_SEQ_1_3(2),
		CLK_COR_SEQ_1_3_3 => CLK_COR_SEQ_1_3(3),
		CLK_COR_SEQ_1_3_4 => CLK_COR_SEQ_1_3(4),
		CLK_COR_SEQ_1_3_5 => CLK_COR_SEQ_1_3(5),
		CLK_COR_SEQ_1_3_6 => CLK_COR_SEQ_1_3(6),
		CLK_COR_SEQ_1_3_7 => CLK_COR_SEQ_1_3(7),
		CLK_COR_SEQ_1_3_8 => CLK_COR_SEQ_1_3(8),
		CLK_COR_SEQ_1_3_9 => CLK_COR_SEQ_1_3(9),
		CLK_COR_SEQ_1_3_10 => CLK_COR_SEQ_1_3(10),
		CLK_COR_SEQ_1_4_0 => CLK_COR_SEQ_1_4(0),
		CLK_COR_SEQ_1_4_1 => CLK_COR_SEQ_1_4(1),
		CLK_COR_SEQ_1_4_2 => CLK_COR_SEQ_1_4(2),
		CLK_COR_SEQ_1_4_3 => CLK_COR_SEQ_1_4(3),
		CLK_COR_SEQ_1_4_4 => CLK_COR_SEQ_1_4(4),
		CLK_COR_SEQ_1_4_5 => CLK_COR_SEQ_1_4(5),
		CLK_COR_SEQ_1_4_6 => CLK_COR_SEQ_1_4(6),
		CLK_COR_SEQ_1_4_7 => CLK_COR_SEQ_1_4(7),
		CLK_COR_SEQ_1_4_8 => CLK_COR_SEQ_1_4(8),
		CLK_COR_SEQ_1_4_9 => CLK_COR_SEQ_1_4(9),
		CLK_COR_SEQ_1_4_10 => CLK_COR_SEQ_1_4(10),
		CLK_COR_SEQ_2_USE => CLK_COR_SEQ_2_USE,
		CLK_COR_SEQ_2_1_0 => CLK_COR_SEQ_2_1(0),
		CLK_COR_SEQ_2_1_1 => CLK_COR_SEQ_2_1(1),
		CLK_COR_SEQ_2_1_2 => CLK_COR_SEQ_2_1(2),
		CLK_COR_SEQ_2_1_3 => CLK_COR_SEQ_2_1(3),
		CLK_COR_SEQ_2_1_4 => CLK_COR_SEQ_2_1(4),
		CLK_COR_SEQ_2_1_5 => CLK_COR_SEQ_2_1(5),
		CLK_COR_SEQ_2_1_6 => CLK_COR_SEQ_2_1(6),
		CLK_COR_SEQ_2_1_7 => CLK_COR_SEQ_2_1(7),
		CLK_COR_SEQ_2_1_8 => CLK_COR_SEQ_2_1(8),
		CLK_COR_SEQ_2_1_9 => CLK_COR_SEQ_2_1(9),
		CLK_COR_SEQ_2_1_10 => CLK_COR_SEQ_2_1(10),
		CLK_COR_SEQ_2_2_0 => CLK_COR_SEQ_2_2(0),
		CLK_COR_SEQ_2_2_1 => CLK_COR_SEQ_2_2(1),
		CLK_COR_SEQ_2_2_2 => CLK_COR_SEQ_2_2(2),
		CLK_COR_SEQ_2_2_3 => CLK_COR_SEQ_2_2(3),
		CLK_COR_SEQ_2_2_4 => CLK_COR_SEQ_2_2(4),
		CLK_COR_SEQ_2_2_5 => CLK_COR_SEQ_2_2(5),
		CLK_COR_SEQ_2_2_6 => CLK_COR_SEQ_2_2(6),
		CLK_COR_SEQ_2_2_7 => CLK_COR_SEQ_2_2(7),
		CLK_COR_SEQ_2_2_8 => CLK_COR_SEQ_2_2(8),
		CLK_COR_SEQ_2_2_9 => CLK_COR_SEQ_2_2(9),
		CLK_COR_SEQ_2_2_10 => CLK_COR_SEQ_2_2(10),
		CLK_COR_SEQ_2_3_0 => CLK_COR_SEQ_2_3(0),
		CLK_COR_SEQ_2_3_1 => CLK_COR_SEQ_2_3(1),
		CLK_COR_SEQ_2_3_2 => CLK_COR_SEQ_2_3(2),
		CLK_COR_SEQ_2_3_3 => CLK_COR_SEQ_2_3(3),
		CLK_COR_SEQ_2_3_4 => CLK_COR_SEQ_2_3(4),
		CLK_COR_SEQ_2_3_5 => CLK_COR_SEQ_2_3(5),
		CLK_COR_SEQ_2_3_6 => CLK_COR_SEQ_2_3(6),
		CLK_COR_SEQ_2_3_7 => CLK_COR_SEQ_2_3(7),
		CLK_COR_SEQ_2_3_8 => CLK_COR_SEQ_2_3(8),
		CLK_COR_SEQ_2_3_9 => CLK_COR_SEQ_2_3(9),
		CLK_COR_SEQ_2_3_10 => CLK_COR_SEQ_2_3(10),
		CLK_COR_SEQ_2_4_0 => CLK_COR_SEQ_2_4(0),
		CLK_COR_SEQ_2_4_1 => CLK_COR_SEQ_2_4(1),
		CLK_COR_SEQ_2_4_2 => CLK_COR_SEQ_2_4(2),
		CLK_COR_SEQ_2_4_3 => CLK_COR_SEQ_2_4(3),
		CLK_COR_SEQ_2_4_4 => CLK_COR_SEQ_2_4(4),
		CLK_COR_SEQ_2_4_5 => CLK_COR_SEQ_2_4(5),
		CLK_COR_SEQ_2_4_6 => CLK_COR_SEQ_2_4(6),
		CLK_COR_SEQ_2_4_7 => CLK_COR_SEQ_2_4(7),
		CLK_COR_SEQ_2_4_8 => CLK_COR_SEQ_2_4(8),
		CLK_COR_SEQ_2_4_9 => CLK_COR_SEQ_2_4(9),
		CLK_COR_SEQ_2_4_10 => CLK_COR_SEQ_2_4(10),
		CHAN_BOND_MODE_0 => CHAN_BOND_MODE(0),
		CHAN_BOND_MODE_1 => CHAN_BOND_MODE(1),
		CHAN_BOND_SEQ_LEN_0 => CHAN_BOND_SEQ_LEN(0),
		CHAN_BOND_SEQ_LEN_1 => CHAN_BOND_SEQ_LEN(1),
		CHAN_BOND_SEQ_1_1_0 => CHAN_BOND_SEQ_1_1(0),
		CHAN_BOND_SEQ_1_1_1 => CHAN_BOND_SEQ_1_1(1),
		CHAN_BOND_SEQ_1_1_2 => CHAN_BOND_SEQ_1_1(2),
		CHAN_BOND_SEQ_1_1_3 => CHAN_BOND_SEQ_1_1(3),
		CHAN_BOND_SEQ_1_1_4 => CHAN_BOND_SEQ_1_1(4),
		CHAN_BOND_SEQ_1_1_5 => CHAN_BOND_SEQ_1_1(5),
		CHAN_BOND_SEQ_1_1_6 => CHAN_BOND_SEQ_1_1(6),
		CHAN_BOND_SEQ_1_1_7 => CHAN_BOND_SEQ_1_1(7),
		CHAN_BOND_SEQ_1_1_8 => CHAN_BOND_SEQ_1_1(8),
		CHAN_BOND_SEQ_1_1_9 => CHAN_BOND_SEQ_1_1(9),
		CHAN_BOND_SEQ_1_1_10 => CHAN_BOND_SEQ_1_1(10),
		CHAN_BOND_SEQ_1_2_0 => CHAN_BOND_SEQ_1_2(0),
		CHAN_BOND_SEQ_1_2_1 => CHAN_BOND_SEQ_1_2(1),
		CHAN_BOND_SEQ_1_2_2 => CHAN_BOND_SEQ_1_2(2),
		CHAN_BOND_SEQ_1_2_3 => CHAN_BOND_SEQ_1_2(3),
		CHAN_BOND_SEQ_1_2_4 => CHAN_BOND_SEQ_1_2(4),
		CHAN_BOND_SEQ_1_2_5 => CHAN_BOND_SEQ_1_2(5),
		CHAN_BOND_SEQ_1_2_6 => CHAN_BOND_SEQ_1_2(6),
		CHAN_BOND_SEQ_1_2_7 => CHAN_BOND_SEQ_1_2(7),
		CHAN_BOND_SEQ_1_2_8 => CHAN_BOND_SEQ_1_2(8),
		CHAN_BOND_SEQ_1_2_9 => CHAN_BOND_SEQ_1_2(9),
		CHAN_BOND_SEQ_1_2_10 => CHAN_BOND_SEQ_1_2(10),
		CHAN_BOND_SEQ_1_3_0 => CHAN_BOND_SEQ_1_3(0),
		CHAN_BOND_SEQ_1_3_1 => CHAN_BOND_SEQ_1_3(1),
		CHAN_BOND_SEQ_1_3_2 => CHAN_BOND_SEQ_1_3(2),
		CHAN_BOND_SEQ_1_3_3 => CHAN_BOND_SEQ_1_3(3),
		CHAN_BOND_SEQ_1_3_4 => CHAN_BOND_SEQ_1_3(4),
		CHAN_BOND_SEQ_1_3_5 => CHAN_BOND_SEQ_1_3(5),
		CHAN_BOND_SEQ_1_3_6 => CHAN_BOND_SEQ_1_3(6),
		CHAN_BOND_SEQ_1_3_7 => CHAN_BOND_SEQ_1_3(7),
		CHAN_BOND_SEQ_1_3_8 => CHAN_BOND_SEQ_1_3(8),
		CHAN_BOND_SEQ_1_3_9 => CHAN_BOND_SEQ_1_3(9),
		CHAN_BOND_SEQ_1_3_10 => CHAN_BOND_SEQ_1_3(10),
		CHAN_BOND_SEQ_1_4_0 => CHAN_BOND_SEQ_1_4(0),
		CHAN_BOND_SEQ_1_4_1 => CHAN_BOND_SEQ_1_4(1),
		CHAN_BOND_SEQ_1_4_2 => CHAN_BOND_SEQ_1_4(2),
		CHAN_BOND_SEQ_1_4_3 => CHAN_BOND_SEQ_1_4(3),
		CHAN_BOND_SEQ_1_4_4 => CHAN_BOND_SEQ_1_4(4),
		CHAN_BOND_SEQ_1_4_5 => CHAN_BOND_SEQ_1_4(5),
		CHAN_BOND_SEQ_1_4_6 => CHAN_BOND_SEQ_1_4(6),
		CHAN_BOND_SEQ_1_4_7 => CHAN_BOND_SEQ_1_4(7),
		CHAN_BOND_SEQ_1_4_8 => CHAN_BOND_SEQ_1_4(8),
		CHAN_BOND_SEQ_1_4_9 => CHAN_BOND_SEQ_1_4(9),
		CHAN_BOND_SEQ_1_4_10 => CHAN_BOND_SEQ_1_4(10),
		CHAN_BOND_SEQ_2_USE => CHAN_BOND_SEQ_2_USE,
		CHAN_BOND_SEQ_2_1_0 => CHAN_BOND_SEQ_2_1(0),
		CHAN_BOND_SEQ_2_1_1 => CHAN_BOND_SEQ_2_1(1),
		CHAN_BOND_SEQ_2_1_2 => CHAN_BOND_SEQ_2_1(2),
		CHAN_BOND_SEQ_2_1_3 => CHAN_BOND_SEQ_2_1(3),
		CHAN_BOND_SEQ_2_1_4 => CHAN_BOND_SEQ_2_1(4),
		CHAN_BOND_SEQ_2_1_5 => CHAN_BOND_SEQ_2_1(5),
		CHAN_BOND_SEQ_2_1_6 => CHAN_BOND_SEQ_2_1(6),
		CHAN_BOND_SEQ_2_1_7 => CHAN_BOND_SEQ_2_1(7),
		CHAN_BOND_SEQ_2_1_8 => CHAN_BOND_SEQ_2_1(8),
		CHAN_BOND_SEQ_2_1_9 => CHAN_BOND_SEQ_2_1(9),
		CHAN_BOND_SEQ_2_1_10 => CHAN_BOND_SEQ_2_1(10),
		CHAN_BOND_SEQ_2_2_0 => CHAN_BOND_SEQ_2_2(0),
		CHAN_BOND_SEQ_2_2_1 => CHAN_BOND_SEQ_2_2(1),
		CHAN_BOND_SEQ_2_2_2 => CHAN_BOND_SEQ_2_2(2),
		CHAN_BOND_SEQ_2_2_3 => CHAN_BOND_SEQ_2_2(3),
		CHAN_BOND_SEQ_2_2_4 => CHAN_BOND_SEQ_2_2(4),
		CHAN_BOND_SEQ_2_2_5 => CHAN_BOND_SEQ_2_2(5),
		CHAN_BOND_SEQ_2_2_6 => CHAN_BOND_SEQ_2_2(6),
		CHAN_BOND_SEQ_2_2_7 => CHAN_BOND_SEQ_2_2(7),
		CHAN_BOND_SEQ_2_2_8 => CHAN_BOND_SEQ_2_2(8),
		CHAN_BOND_SEQ_2_2_9 => CHAN_BOND_SEQ_2_2(9),
		CHAN_BOND_SEQ_2_2_10 => CHAN_BOND_SEQ_2_2(10),
		CHAN_BOND_SEQ_2_3_0 => CHAN_BOND_SEQ_2_3(0),
		CHAN_BOND_SEQ_2_3_1 => CHAN_BOND_SEQ_2_3(1),
		CHAN_BOND_SEQ_2_3_2 => CHAN_BOND_SEQ_2_3(2),
		CHAN_BOND_SEQ_2_3_3 => CHAN_BOND_SEQ_2_3(3),
		CHAN_BOND_SEQ_2_3_4 => CHAN_BOND_SEQ_2_3(4),
		CHAN_BOND_SEQ_2_3_5 => CHAN_BOND_SEQ_2_3(5),
		CHAN_BOND_SEQ_2_3_6 => CHAN_BOND_SEQ_2_3(6),
		CHAN_BOND_SEQ_2_3_7 => CHAN_BOND_SEQ_2_3(7),
		CHAN_BOND_SEQ_2_3_8 => CHAN_BOND_SEQ_2_3(8),
		CHAN_BOND_SEQ_2_3_9 => CHAN_BOND_SEQ_2_3(9),
		CHAN_BOND_SEQ_2_3_10 => CHAN_BOND_SEQ_2_3(10),
		CHAN_BOND_SEQ_2_4_0 => CHAN_BOND_SEQ_2_4(0),
		CHAN_BOND_SEQ_2_4_1 => CHAN_BOND_SEQ_2_4(1),
		CHAN_BOND_SEQ_2_4_2 => CHAN_BOND_SEQ_2_4(2),
		CHAN_BOND_SEQ_2_4_3 => CHAN_BOND_SEQ_2_4(3),
		CHAN_BOND_SEQ_2_4_4 => CHAN_BOND_SEQ_2_4(4),
		CHAN_BOND_SEQ_2_4_5 => CHAN_BOND_SEQ_2_4(5),
		CHAN_BOND_SEQ_2_4_6 => CHAN_BOND_SEQ_2_4(6),
		CHAN_BOND_SEQ_2_4_7 => CHAN_BOND_SEQ_2_4(7),
		CHAN_BOND_SEQ_2_4_8 => CHAN_BOND_SEQ_2_4(8),
		CHAN_BOND_SEQ_2_4_9 => CHAN_BOND_SEQ_2_4(9),
		CHAN_BOND_SEQ_2_4_10 => CHAN_BOND_SEQ_2_4(10),
		CHAN_BOND_WAIT_0 => CHAN_BOND_WAIT(0),
		CHAN_BOND_WAIT_1 => CHAN_BOND_WAIT(1),
		CHAN_BOND_WAIT_2 => CHAN_BOND_WAIT(2),
		CHAN_BOND_WAIT_3 => CHAN_BOND_WAIT(3),
		CHAN_BOND_OFFSET_0 => CHAN_BOND_OFFSET(0),
		CHAN_BOND_OFFSET_1 => CHAN_BOND_OFFSET(1),
		CHAN_BOND_OFFSET_2 => CHAN_BOND_OFFSET(2),
		CHAN_BOND_OFFSET_3 => CHAN_BOND_OFFSET(3),
		RX_DATA_WIDTH_0 => RX_DATA_WIDTH(0),
		RX_DATA_WIDTH_1 => RX_DATA_WIDTH(1),
		TX_DATA_WIDTH_0 => TX_DATA_WIDTH(0),
		TX_DATA_WIDTH_1 => TX_DATA_WIDTH(1),
		BREFCLK => BREFCLK,
		BREFCLK2 => BREFCLK2,
		REF_CLK_V_SEL => REF_CLK_V_SEL
	);

begin -- GT_SWIFT_BUS
gt_swift_inst : GT_SWIFT
	port map (
		TX_CRC_FORCE_VALUE => TX_CRC_FORCE_VALUE,
		TXFORCECRCERR => TXFORCECRCERR,
		RX_CRC_USE => RX_CRC_USE,
		TX_CRC_USE => TX_CRC_USE,
		CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT,
		CONFIGENABLE => CONFIGENABLE,
		CONFIGIN => CONFIGIN,
		CONFIGOUT => CONFIGOUT,
		CRC_END_OF_PKT => CRC_END_OF_PKT,
		CRC_FORMAT => CRC_FORMAT,
		CRC_START_OF_PKT => CRC_START_OF_PKT,
		CHAN_BOND_LIMIT => CHAN_BOND_LIMIT,
		ALIGN_COMMA_MSB => ALIGN_COMMA_MSB,
		CHAN_BOND_MODE => CHAN_BOND_MODE,
		CHAN_BOND_OFFSET => CHAN_BOND_OFFSET,
		CHAN_BOND_SEQ_1_1 => CHAN_BOND_SEQ_1_1,
		CHAN_BOND_SEQ_1_2 => CHAN_BOND_SEQ_1_2,
		CHAN_BOND_SEQ_1_3 => CHAN_BOND_SEQ_1_3,
		CHAN_BOND_SEQ_1_4 => CHAN_BOND_SEQ_1_4,
		CHAN_BOND_SEQ_2_1 => CHAN_BOND_SEQ_2_1,
		CHAN_BOND_SEQ_2_2 => CHAN_BOND_SEQ_2_2,
		CHAN_BOND_SEQ_2_3 => CHAN_BOND_SEQ_2_3,
		CHAN_BOND_SEQ_2_4 => CHAN_BOND_SEQ_2_4,
		CHAN_BOND_SEQ_2_USE => CHAN_BOND_SEQ_2_USE,
		CHAN_BOND_SEQ_LEN => CHAN_BOND_SEQ_LEN,
		CHAN_BOND_WAIT => CHAN_BOND_WAIT,
		CHBONDDONE => CHBONDDONE,
		CHBONDI => CHBONDI,
		CHBONDO => CHBONDO,
		CLK_COR_INSERT_IDLE_FLAG => CLK_COR_INSERT_IDLE_FLAG,
		CLK_COR_KEEP_IDLE => CLK_COR_KEEP_IDLE,
		CLK_COR_REPEAT_WAIT => CLK_COR_REPEAT_WAIT,
		CLK_COR_SEQ_1_1 => CLK_COR_SEQ_1_1,
		CLK_COR_SEQ_1_2 => CLK_COR_SEQ_1_2,
		CLK_COR_SEQ_1_3 => CLK_COR_SEQ_1_3,
		CLK_COR_SEQ_1_4 => CLK_COR_SEQ_1_4,
		CLK_COR_SEQ_2_1 => CLK_COR_SEQ_2_1,
		CLK_COR_SEQ_2_2 => CLK_COR_SEQ_2_2,
		CLK_COR_SEQ_2_3 => CLK_COR_SEQ_2_3,
		CLK_COR_SEQ_2_4 => CLK_COR_SEQ_2_4,
		CLK_COR_SEQ_2_USE => CLK_COR_SEQ_2_USE,
		CLK_COR_SEQ_LEN => CLK_COR_SEQ_LEN,
		CLK_CORRECT_USE => CLK_CORRECT_USE,
		COMMA_10B_MASK => COMMA_10B_MASK,
		DEC_MCOMMA_DETECT => DEC_MCOMMA_DETECT,
		DEC_PCOMMA_DETECT => DEC_PCOMMA_DETECT,
		DEC_VALID_COMMA_ONLY => DEC_VALID_COMMA_ONLY,
		ENCHANSYNC => ENCHANSYNC,
		LOOPBACK => LOOPBACK,
		MCOMMA_10B_VALUE => MCOMMA_10B_VALUE,
		MCOMMA_DETECT => MCOMMA_DETECT,
		PCOMMA_10B_VALUE => PCOMMA_10B_VALUE,
		PCOMMA_DETECT => PCOMMA_DETECT,
		POWERDOWN => POWERDOWN,
		GSR => GSR,
		REFCLK => REFCLK,
		REFCLK2 => REFCLK2,
		REFCLKSEL => REFCLKSEL,
		RX_BUFFER_USE => RX_BUFFER_USE,
		RX_DATA_WIDTH => RX_DATA_WIDTH,
		RX_DECODE_USE => RX_DECODE_USE,
		RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM,
		RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR,
		RX_LOS_THRESHOLD => RX_LOS_THRESHOLD,
		RXN => RXN,
		RXP => RXP,
		RXLOSSOFSYNC => RXLOSSOFSYNC,
		RXCLKCORCNT => RXCLKCORCNT,
		RXBUFSTATUS => RXBUFSTATUS,
		RXCHARISCOMMA => RXCHARISCOMMA,
		RXCHARISK => RXCHARISK,
		RXCOMMADET => RXCOMMADET,
		RXDATA => RXDATA,
		RXDISPERR => RXDISPERR,
		RXNOTINTABLE => RXNOTINTABLE,
		RXCHECKINGCRC => RXCHECKINGCRC,
		RXCRCERR => RXCRCERR,
		RXPOLARITY => RXPOLARITY,
		RXREALIGN => RXREALIGN,
		RXRECCLK => RXRECCLK,
		RXRESET => RXRESET,
		RXRUNDISP => RXRUNDISP,
		RXUSRCLK => RXUSRCLK,
		RXUSRCLK2 => RXUSRCLK2,
		TX_DIFF_CTRL => TX_DIFF_CTRL,
		TX_PREEMPHASIS => TX_PREEMPHASIS,
		TERMINATION_IMP => TERMINATION_IMP,
		SERDES_10B => SERDES_10B,
		TX_BUFFER_USE => TX_BUFFER_USE,
		TX_DATA_WIDTH => TX_DATA_WIDTH,
		TXBUFERR => TXBUFERR,
		TXBYPASS8B10B => TXBYPASS8B10B,
		TXCHARDISPMODE => TXCHARDISPMODE,
		TXCHARDISPVAL => TXCHARDISPVAL,
		TXCHARISK => TXCHARISK,
		TXDATA => TXDATA,
		TXKERR => TXKERR,
		TXN => TXN,
		TXP => TXP,
		TXINHIBIT => TXINHIBIT,
		TXPOLARITY => TXPOLARITY,
		TXRESET => TXRESET,
		TXRUNDISP => TXRUNDISP,
		TXUSRCLK => TXUSRCLK,
		TXUSRCLK2 => TXUSRCLK2,
		ENMCOMMAALIGN => ENMCOMMAALIGN,
		ENPCOMMAALIGN => ENPCOMMAALIGN,
		BREFCLK => BREFCLK,
		BREFCLK2 => BREFCLK2,
		REF_CLK_V_SEL => REF_CLK_V_SEL
);
end GT_SWIFT_BUS_v;

----------------------------------------------------
--  
--  Library Name :  unisim
--  Unit    Name :  GT
--  Unit    Type :  Text Unit
--  
------------------------------------------------------


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/gt.vhd,v 1.4 2004/04/08 18:46:22 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 7.1i (H.19)
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Gigabit Transceiver for High-Speed I/O Simulation Model
-- /___/   /\     Filename : GT.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:07 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL GT -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;

library unisim;
use unisim.VCOMPONENTS.all;

entity GT is
generic (
                in_delay : time := 0 ps;
                out_delay : VitalDelayType01 := (100 ps, 100 ps);        

		ALIGN_COMMA_MSB : boolean := FALSE;
		CHAN_BOND_LIMIT : integer := 16;
		CHAN_BOND_MODE : string := "OFF";
		CHAN_BOND_OFFSET : integer := 8;
		CHAN_BOND_ONE_SHOT : boolean := FALSE;
		CHAN_BOND_SEQ_1_1 : bit_vector := "00000000000";
		CHAN_BOND_SEQ_1_2 : bit_vector := "00000000000";
		CHAN_BOND_SEQ_1_3 : bit_vector := "00000000000";
		CHAN_BOND_SEQ_1_4 : bit_vector := "00000000000";
		CHAN_BOND_SEQ_2_1 : bit_vector := "00000000000";
		CHAN_BOND_SEQ_2_2 : bit_vector := "00000000000";
		CHAN_BOND_SEQ_2_3 : bit_vector := "00000000000";
		CHAN_BOND_SEQ_2_4 : bit_vector := "00000000000";
		CHAN_BOND_SEQ_2_USE : boolean := FALSE;
		CHAN_BOND_SEQ_LEN : integer := 1;
		CHAN_BOND_WAIT : integer := 8;
		CLK_COR_INSERT_IDLE_FLAG : boolean := FALSE;
		CLK_COR_KEEP_IDLE : boolean := FALSE;
		CLK_COR_REPEAT_WAIT : integer := 1;
		CLK_COR_SEQ_1_1 : bit_vector := "00000000000";
		CLK_COR_SEQ_1_2 : bit_vector := "00000000000";
		CLK_COR_SEQ_1_3 : bit_vector := "00000000000";
		CLK_COR_SEQ_1_4 : bit_vector := "00000000000";
		CLK_COR_SEQ_2_1 : bit_vector := "00000000000";
		CLK_COR_SEQ_2_2 : bit_vector := "00000000000";
		CLK_COR_SEQ_2_3 : bit_vector := "00000000000";
		CLK_COR_SEQ_2_4 : bit_vector := "00000000000";
		CLK_COR_SEQ_2_USE : boolean := FALSE;
		CLK_COR_SEQ_LEN : integer := 1;
		CLK_CORRECT_USE : boolean := TRUE;
		COMMA_10B_MASK : bit_vector := "1111111000";
		CRC_END_OF_PKT : string := "K29_7";
		CRC_FORMAT : string := "USER_MODE";
		CRC_START_OF_PKT : string := "K27_7";
		DEC_MCOMMA_DETECT : boolean := TRUE;
		DEC_PCOMMA_DETECT : boolean := TRUE;
		DEC_VALID_COMMA_ONLY : boolean := TRUE;
		MCOMMA_10B_VALUE : bit_vector := "1100000000";
		MCOMMA_DETECT : boolean := TRUE;
		PCOMMA_10B_VALUE : bit_vector := "0011111000";
		PCOMMA_DETECT : boolean := TRUE;
		REF_CLK_V_SEL : integer := 0;
		RX_BUFFER_USE : boolean := TRUE;
		RX_CRC_USE : boolean := FALSE;
		RX_DATA_WIDTH : integer := 2;
		RX_DECODE_USE : boolean := TRUE;
		RX_LOS_INVALID_INCR : integer := 1;
		RX_LOS_THRESHOLD : integer := 4;
		RX_LOSS_OF_SYNC_FSM : boolean := TRUE;
		SERDES_10B : boolean := FALSE;
		TERMINATION_IMP : integer := 50;
		TX_BUFFER_USE : boolean := TRUE;
		TX_CRC_FORCE_VALUE : bit_vector := "11010110";
		TX_CRC_USE : boolean := FALSE;
		TX_DATA_WIDTH : integer := 2;
		TX_DIFF_CTRL : integer := 500;
		TX_PREEMPHASIS : integer := 0

  );

port (
		CHBONDDONE : out std_ulogic;
		CHBONDO : out std_logic_vector(3 downto 0);
		CONFIGOUT : out std_ulogic;
		RXBUFSTATUS : out std_logic_vector(1 downto 0);
		RXCHARISCOMMA : out std_logic_vector(3 downto 0);
		RXCHARISK : out std_logic_vector(3 downto 0);
		RXCHECKINGCRC : out std_ulogic;
		RXCLKCORCNT : out std_logic_vector(2 downto 0);
		RXCOMMADET : out std_ulogic;
		RXCRCERR : out std_ulogic;
		RXDATA : out std_logic_vector(31 downto 0);
		RXDISPERR : out std_logic_vector(3 downto 0);
		RXLOSSOFSYNC : out std_logic_vector(1 downto 0);
		RXNOTINTABLE : out std_logic_vector(3 downto 0);
		RXREALIGN : out std_ulogic;
		RXRECCLK : out std_ulogic;
		RXRUNDISP : out std_logic_vector(3 downto 0);
		TXBUFERR : out std_ulogic;
		TXKERR : out std_logic_vector(3 downto 0);
		TXN : out std_ulogic;
		TXP : out std_ulogic;
		TXRUNDISP : out std_logic_vector(3 downto 0);

		BREFCLK : in std_ulogic := 'X';
		BREFCLK2 : in std_ulogic := 'X';
		CHBONDI : in std_logic_vector(3 downto 0);
		CONFIGENABLE : in std_ulogic;
		CONFIGIN : in std_ulogic;
		ENCHANSYNC : in std_ulogic;
		ENMCOMMAALIGN : in std_ulogic;
		ENPCOMMAALIGN : in std_ulogic;
		LOOPBACK : in std_logic_vector(1 downto 0);
		POWERDOWN : in std_ulogic;
		REFCLK : in std_ulogic;
		REFCLK2 : in std_ulogic;
		REFCLKSEL : in std_ulogic;
		RXN : in std_ulogic;
		RXP : in std_ulogic;
		RXPOLARITY : in std_ulogic;
		RXRESET : in std_ulogic;
		RXUSRCLK : in std_ulogic;
		RXUSRCLK2 : in std_ulogic;
		TXBYPASS8B10B : in std_logic_vector(3 downto 0);
		TXCHARDISPMODE : in std_logic_vector(3 downto 0);
		TXCHARDISPVAL : in std_logic_vector(3 downto 0);
		TXCHARISK : in std_logic_vector(3 downto 0);
		TXDATA : in std_logic_vector(31 downto 0);
		TXFORCECRCERR : in std_ulogic;
		TXINHIBIT : in std_ulogic;
		TXPOLARITY : in std_ulogic;
		TXRESET : in std_ulogic;
		TXUSRCLK : in std_ulogic;
		TXUSRCLK2 : in std_ulogic
     );
end GT;



-- Architecture body --

architecture GT_V of GT is

  component gt_swift_bus
	port (
		TX_CRC_FORCE_VALUE : in std_logic_vector(7 downto 0);
		RXLOSSOFSYNC : out std_logic_vector(1 downto 0);
		RXCLKCORCNT : out std_logic_vector(2 downto 0);
		RXP : in std_ulogic;
		RXN : in std_ulogic;
		GSR : in std_ulogic;
		TXP : out std_ulogic;
		TXN : out std_ulogic;
		CONFIGENABLE : in std_ulogic;
		CONFIGIN : in std_ulogic;
		CONFIGOUT : out std_ulogic;
		ENMCOMMAALIGN : in std_ulogic;
		ENPCOMMAALIGN : in std_ulogic;
		CRC_END_OF_PKT : in std_logic_vector(7 downto 0);
		CRC_FORMAT : in std_logic_vector(1 downto 0);
		CRC_START_OF_PKT : in std_logic_vector(7 downto 0);
		CHAN_BOND_LIMIT : in std_logic_vector(4 downto 0);
		REFCLK : in std_ulogic;
		REFCLK2 : in std_ulogic;
		REFCLKSEL : in std_ulogic;
		RXUSRCLK : in std_ulogic;
		TXUSRCLK : in std_ulogic;
		RXUSRCLK2 : in std_ulogic;
		TXUSRCLK2 : in std_ulogic;
		RXRESET : in std_ulogic;
		TXRESET : in std_ulogic;
		POWERDOWN : in std_ulogic;
		LOOPBACK : in std_logic_vector(1 downto 0);
		TXDATA : in std_logic_vector(31 downto 0);
		RX_LOSS_OF_SYNC_FSM : in std_ulogic;
		RX_LOS_INVALID_INCR : in std_logic_vector(2 downto 0);
		RX_LOS_THRESHOLD : in std_logic_vector(2 downto 0);
		TXCHARDISPMODE : in std_logic_vector(3 downto 0);
		TXCHARDISPVAL : in std_logic_vector(3 downto 0);
		TXCHARISK : in std_logic_vector(3 downto 0);
		TXBYPASS8B10B : in std_logic_vector(3 downto 0);
		TXPOLARITY : in std_ulogic;
		TXINHIBIT : in std_ulogic;
		ENCHANSYNC : in std_ulogic;
		RXPOLARITY : in std_ulogic;
		CHBONDI : in std_logic_vector(3 downto 0);
		RXRECCLK : out std_ulogic;
		TXBUFERR : out std_ulogic;
		TXFORCECRCERR : in std_ulogic;
		TXRUNDISP : out std_logic_vector(3 downto 0);
		TXKERR : out std_logic_vector(3 downto 0);
		RXREALIGN : out std_ulogic;
		RXCOMMADET : out std_ulogic;
		RXCHECKINGCRC : out std_ulogic;
		RXCRCERR : out std_ulogic;
		RXDATA : out std_logic_vector(31 downto 0);
		RXCHARISCOMMA : out std_logic_vector(3 downto 0);
		RXCHARISK : out std_logic_vector(3 downto 0);
		RXNOTINTABLE : out std_logic_vector(3 downto 0);
		RXDISPERR : out std_logic_vector(3 downto 0);
		RXRUNDISP : out std_logic_vector(3 downto 0);
		RXBUFSTATUS : out std_logic_vector(1 downto 0);
		CHBONDO : out std_logic_vector(3 downto 0);
		CHBONDDONE : out std_ulogic;
		TX_PREEMPHASIS : in std_logic_vector(1 downto 0);
		TX_DIFF_CTRL : in std_logic_vector(2 downto 0);
		TERMINATION_IMP : in std_ulogic;
		SERDES_10B : in std_ulogic;
		ALIGN_COMMA_MSB : in std_ulogic;
		PCOMMA_DETECT : in std_ulogic;
		MCOMMA_DETECT : in std_ulogic;
		PCOMMA_10B_VALUE : in std_logic_vector(0 to 9);
		MCOMMA_10B_VALUE : in std_logic_vector(0 to 9);
		COMMA_10B_MASK : in std_logic_vector(0 to 9);
		DEC_PCOMMA_DETECT : in std_ulogic;
		DEC_MCOMMA_DETECT : in std_ulogic;
		DEC_VALID_COMMA_ONLY : in std_ulogic;
		RX_DECODE_USE : in std_ulogic;
		RX_BUFFER_USE : in std_ulogic;
		TX_BUFFER_USE : in std_ulogic;
		CLK_CORRECT_USE : in std_ulogic;
		CLK_COR_SEQ_LEN : in std_logic_vector(1 downto 0);
		CLK_COR_INSERT_IDLE_FLAG : in std_ulogic;
		CLK_COR_KEEP_IDLE : in std_ulogic;
		CLK_COR_REPEAT_WAIT : in std_logic_vector(4 downto 0);
		CLK_COR_SEQ_1_1 : in std_logic_vector(10 downto 0);
		CLK_COR_SEQ_1_2 : in std_logic_vector(10 downto 0);
		CLK_COR_SEQ_1_3 : in std_logic_vector(10 downto 0);
		CLK_COR_SEQ_1_4 : in std_logic_vector(10 downto 0);
		CLK_COR_SEQ_2_USE : in std_ulogic;
		CLK_COR_SEQ_2_1 : in std_logic_vector(10 downto 0);
		CLK_COR_SEQ_2_2 : in std_logic_vector(10 downto 0);
		CLK_COR_SEQ_2_3 : in std_logic_vector(10 downto 0);
		CLK_COR_SEQ_2_4 : in std_logic_vector(10 downto 0);
		CHAN_BOND_MODE : in std_logic_vector(1 downto 0);
		CHAN_BOND_SEQ_LEN : in std_logic_vector(1 downto 0);
		CHAN_BOND_SEQ_1_1 : in std_logic_vector(10 downto 0);
		CHAN_BOND_SEQ_1_2 : in std_logic_vector(10 downto 0);
		CHAN_BOND_SEQ_1_3 : in std_logic_vector(10 downto 0);
		CHAN_BOND_SEQ_1_4 : in std_logic_vector(10 downto 0);
		CHAN_BOND_SEQ_2_USE : in std_ulogic;
		CHAN_BOND_SEQ_2_1 : in std_logic_vector(10 downto 0);
		CHAN_BOND_SEQ_2_2 : in std_logic_vector(10 downto 0);
		CHAN_BOND_SEQ_2_3 : in std_logic_vector(10 downto 0);
		CHAN_BOND_SEQ_2_4 : in std_logic_vector(10 downto 0);
		CHAN_BOND_WAIT : in std_logic_vector(3 downto 0);
		CHAN_BOND_OFFSET : in std_logic_vector(3 downto 0);
		TX_CRC_USE : in std_ulogic;
		RX_CRC_USE : in std_ulogic;
		CHAN_BOND_ONE_SHOT : in std_ulogic;
		RX_DATA_WIDTH : in std_logic_vector(1 downto 0);
		TX_DATA_WIDTH : in std_logic_vector(1 downto 0);
		BREFCLK : in std_ulogic;
		BREFCLK2 : in std_ulogic;
		REF_CLK_V_SEL : in std_ulogic
	);    
  end component;
-- Attribute-to-Cell mapping signals
        signal   ALIGN_COMMA_MSB_BINARY  :  std_ulogic;
        signal   CHAN_BOND_LIMIT_BINARY  :  std_logic_vector(4 downto 0);
        signal   CHAN_BOND_MODE_BINARY  :  std_logic_vector(1 downto 0);
        signal   CHAN_BOND_OFFSET_BINARY  :  std_logic_vector(3 downto 0);
        signal   CHAN_BOND_ONE_SHOT_BINARY  :  std_ulogic;
        signal   CHAN_BOND_SEQ_1_1_BINARY  :  std_logic_vector(10 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_1);
        signal   CHAN_BOND_SEQ_1_2_BINARY  :  std_logic_vector(10 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_2);
        signal   CHAN_BOND_SEQ_1_3_BINARY  :  std_logic_vector(10 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_3);
        signal   CHAN_BOND_SEQ_1_4_BINARY  :  std_logic_vector(10 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_4);
        signal   CHAN_BOND_SEQ_2_1_BINARY  :  std_logic_vector(10 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_1);
        signal   CHAN_BOND_SEQ_2_2_BINARY  :  std_logic_vector(10 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_2);
        signal   CHAN_BOND_SEQ_2_3_BINARY  :  std_logic_vector(10 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_3);
        signal   CHAN_BOND_SEQ_2_4_BINARY  :  std_logic_vector(10 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_4);
        signal   CHAN_BOND_SEQ_2_USE_BINARY  :  std_ulogic;
        signal   CHAN_BOND_SEQ_LEN_BINARY  :  std_logic_vector(1 downto 0);
        signal   CHAN_BOND_WAIT_BINARY  :  std_logic_vector(3 downto 0);
        signal   CLK_COR_INSERT_IDLE_FLAG_BINARY  :  std_ulogic;
        signal   CLK_COR_KEEP_IDLE_BINARY  :  std_ulogic;
        signal   CLK_COR_REPEAT_WAIT_BINARY  :  std_logic_vector(4 downto 0);
        signal   CLK_COR_SEQ_1_1_BINARY  :  std_logic_vector(10 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_1);
        signal   CLK_COR_SEQ_1_2_BINARY  :  std_logic_vector(10 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_2);
        signal   CLK_COR_SEQ_1_3_BINARY  :  std_logic_vector(10 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_3);
        signal   CLK_COR_SEQ_1_4_BINARY  :  std_logic_vector(10 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_4);
        signal   CLK_COR_SEQ_2_1_BINARY  :  std_logic_vector(10 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_1);
        signal   CLK_COR_SEQ_2_2_BINARY  :  std_logic_vector(10 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_2);
        signal   CLK_COR_SEQ_2_3_BINARY  :  std_logic_vector(10 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_3);
        signal   CLK_COR_SEQ_2_4_BINARY  :  std_logic_vector(10 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_4);
        signal   CLK_COR_SEQ_2_USE_BINARY  :  std_ulogic;
        signal   CLK_COR_SEQ_LEN_BINARY  :  std_logic_vector(1 downto 0);
        signal   CLK_CORRECT_USE_BINARY  :  std_ulogic;
        signal   COMMA_10B_MASK_BINARY  :  std_logic_vector(9 downto 0) := To_StdLogicVector(COMMA_10B_MASK);
        signal   CRC_END_OF_PKT_BINARY  :  std_logic_vector(7 downto 0);
        signal   CRC_FORMAT_BINARY  :  std_logic_vector(1 downto 0);
        signal   CRC_START_OF_PKT_BINARY  :  std_logic_vector(7 downto 0);
        signal   DEC_MCOMMA_DETECT_BINARY  :  std_ulogic;
        signal   DEC_PCOMMA_DETECT_BINARY  :  std_ulogic;
        signal   DEC_VALID_COMMA_ONLY_BINARY  :  std_ulogic;
        signal   MCOMMA_10B_VALUE_BINARY  :  std_logic_vector(9 downto 0) := To_StdLogicVector(MCOMMA_10B_VALUE);
        signal   MCOMMA_DETECT_BINARY  :  std_ulogic;
        signal   PCOMMA_10B_VALUE_BINARY  :  std_logic_vector(9 downto 0) := To_StdLogicVector(PCOMMA_10B_VALUE);
        signal   PCOMMA_DETECT_BINARY  :  std_ulogic;
        signal   REF_CLK_V_SEL_BINARY  :  std_ulogic;
        signal   RX_BUFFER_USE_BINARY  :  std_ulogic;
        signal   RX_CRC_USE_BINARY  :  std_ulogic;
        signal   RX_DATA_WIDTH_BINARY  :  std_logic_vector(1 downto 0);
        signal   RX_DECODE_USE_BINARY  :  std_ulogic;
        signal   RX_LOS_INVALID_INCR_BINARY  :  std_logic_vector(2 downto 0);
        signal   RX_LOS_THRESHOLD_BINARY  :  std_logic_vector(2 downto 0);
        signal   RX_LOSS_OF_SYNC_FSM_BINARY  :  std_ulogic;
        signal   SERDES_10B_BINARY  :  std_ulogic;
        signal   TERMINATION_IMP_BINARY  :  std_ulogic;
        signal   TX_BUFFER_USE_BINARY  :  std_ulogic;
        signal   TX_CRC_FORCE_VALUE_BINARY  :  std_logic_vector(7 downto 0) := To_StdLogicVector(TX_CRC_FORCE_VALUE);
        signal   TX_CRC_USE_BINARY  :  std_ulogic;
        signal   TX_DATA_WIDTH_BINARY  :  std_logic_vector(1 downto 0);
        signal   TX_DIFF_CTRL_BINARY  :  std_logic_vector(2 downto 0);
        signal   TX_PREEMPHASIS_BINARY  :  std_logic_vector(1 downto 0);

-- Input/Output Pin signals
        signal   CHBONDDONE_out  :  std_ulogic;
        signal   CHBONDO_out  :  std_logic_vector(3 downto 0);
        signal   CONFIGOUT_out  :  std_ulogic;
        signal   RXBUFSTATUS_out  :  std_logic_vector(1 downto 0);
        signal   RXCHARISCOMMA_out  :  std_logic_vector(3 downto 0);
        signal   RXCHARISK_out  :  std_logic_vector(3 downto 0);
        signal   RXCHECKINGCRC_out  :  std_ulogic;
        signal   RXCLKCORCNT_out  :  std_logic_vector(2 downto 0);
        signal   RXCOMMADET_out  :  std_ulogic;
        signal   RXCRCERR_out  :  std_ulogic;
        signal   RXDATA_out  :  std_logic_vector(31 downto 0);
        signal   RXDISPERR_out  :  std_logic_vector(3 downto 0);
        signal   RXLOSSOFSYNC_out  :  std_logic_vector(1 downto 0);
        signal   RXNOTINTABLE_out  :  std_logic_vector(3 downto 0);
        signal   RXREALIGN_out  :  std_ulogic;
        signal   RXRECCLK_out  :  std_ulogic;
        signal   RXRUNDISP_out  :  std_logic_vector(3 downto 0);
        signal   TXBUFERR_out  :  std_ulogic;
        signal   TXKERR_out  :  std_logic_vector(3 downto 0);
        signal   TXN_out  :  std_ulogic;
        signal   TXP_out  :  std_ulogic;
        signal   TXRUNDISP_out  :  std_logic_vector(3 downto 0);

        signal   BREFCLK_ipd  :  std_ulogic;
        signal   BREFCLK2_ipd  :  std_ulogic;
        signal   CHBONDI_ipd  :  std_logic_vector(3 downto 0);
        signal   CONFIGENABLE_ipd  :  std_ulogic;
        signal   CONFIGIN_ipd  :  std_ulogic;
        signal   ENCHANSYNC_ipd  :  std_ulogic;
        signal   ENMCOMMAALIGN_ipd  :  std_ulogic;
        signal   ENPCOMMAALIGN_ipd  :  std_ulogic;
        signal   LOOPBACK_ipd  :  std_logic_vector(1 downto 0);
        signal   POWERDOWN_ipd  :  std_ulogic;
        signal   REFCLK_ipd  :  std_ulogic;
        signal   REFCLK2_ipd  :  std_ulogic;
        signal   REFCLKSEL_ipd  :  std_ulogic;
        signal   RXN_ipd  :  std_ulogic;
        signal   RXP_ipd  :  std_ulogic;
        signal   RXPOLARITY_ipd  :  std_ulogic;
        signal   RXRESET_ipd  :  std_ulogic;
        signal   RXUSRCLK_ipd  :  std_ulogic;
        signal   RXUSRCLK2_ipd  :  std_ulogic;
        signal   TXBYPASS8B10B_ipd  :  std_logic_vector(3 downto 0);
        signal   TXCHARDISPMODE_ipd  :  std_logic_vector(3 downto 0);
        signal   TXCHARDISPVAL_ipd  :  std_logic_vector(3 downto 0);
        signal   TXCHARISK_ipd  :  std_logic_vector(3 downto 0);
        signal   TXDATA_ipd  :  std_logic_vector(31 downto 0);
        signal   TXFORCECRCERR_ipd  :  std_ulogic;
        signal   TXINHIBIT_ipd  :  std_ulogic;
        signal   TXPOLARITY_ipd  :  std_ulogic;
        signal   TXRESET_ipd  :  std_ulogic;
        signal   TXUSRCLK_ipd  :  std_ulogic;
        signal   TXUSRCLK2_ipd  :  std_ulogic;


begin

BREFCLK_ipd < = BREFCLK after in_delay;
BREFCLK2_ipd < = BREFCLK2 after in_delay;
CHBONDI_ipd < = CHBONDI after in_delay;
CONFIGENABLE_ipd < = CONFIGENABLE after in_delay;
CONFIGIN_ipd < = CONFIGIN after in_delay;
ENCHANSYNC_ipd < = ENCHANSYNC after in_delay;
ENMCOMMAALIGN_ipd < = ENMCOMMAALIGN after in_delay;
ENPCOMMAALIGN_ipd < = ENPCOMMAALIGN after in_delay;
LOOPBACK_ipd < = LOOPBACK after in_delay;
POWERDOWN_ipd < = POWERDOWN after in_delay;
REFCLK_ipd < = REFCLK after in_delay;
REFCLK2_ipd < = REFCLK2 after in_delay;
REFCLKSEL_ipd < = REFCLKSEL after in_delay;
RXN_ipd < = RXN after in_delay;
RXP_ipd < = RXP after in_delay;
RXPOLARITY_ipd < = RXPOLARITY after in_delay;
RXRESET_ipd < = RXRESET after in_delay;
RXUSRCLK_ipd < = RXUSRCLK after in_delay;
RXUSRCLK2_ipd < = RXUSRCLK2 after in_delay;
TXBYPASS8B10B_ipd < = TXBYPASS8B10B after in_delay;
TXCHARDISPMODE_ipd < = TXCHARDISPMODE after in_delay;
TXCHARDISPVAL_ipd < = TXCHARDISPVAL after in_delay;
TXCHARISK_ipd < = TXCHARISK after in_delay;
TXDATA_ipd < = TXDATA after in_delay;
TXFORCECRCERR_ipd < = TXFORCECRCERR after in_delay;
TXINHIBIT_ipd < = TXINHIBIT after in_delay;
TXPOLARITY_ipd < = TXPOLARITY after in_delay;
TXRESET_ipd < = TXRESET after in_delay;
TXUSRCLK_ipd < = TXUSRCLK after in_delay;
TXUSRCLK2_ipd < = TXUSRCLK2 after in_delay;

   gt_swift_bw_1 : GT_SWIFT_BUS
      port map (
          ALIGN_COMMA_MSB  =>  ALIGN_COMMA_MSB_BINARY,
          BREFCLK  =>  BREFCLK_ipd,
          BREFCLK2  =>  BREFCLK2_ipd,
          CHAN_BOND_LIMIT  =>  CHAN_BOND_LIMIT_BINARY,
          CHAN_BOND_MODE  =>  CHAN_BOND_MODE_BINARY,
          CHAN_BOND_OFFSET  =>  CHAN_BOND_OFFSET_BINARY,
          CHAN_BOND_ONE_SHOT  =>  CHAN_BOND_ONE_SHOT_BINARY,
          CHAN_BOND_SEQ_1_1  =>  CHAN_BOND_SEQ_1_1_BINARY,
          CHAN_BOND_SEQ_1_2  =>  CHAN_BOND_SEQ_1_2_BINARY,
          CHAN_BOND_SEQ_1_3  =>  CHAN_BOND_SEQ_1_3_BINARY,
          CHAN_BOND_SEQ_1_4  =>  CHAN_BOND_SEQ_1_4_BINARY,
          CHAN_BOND_SEQ_2_1  =>  CHAN_BOND_SEQ_2_1_BINARY,
          CHAN_BOND_SEQ_2_2  =>  CHAN_BOND_SEQ_2_2_BINARY,
          CHAN_BOND_SEQ_2_3  =>  CHAN_BOND_SEQ_2_3_BINARY,
          CHAN_BOND_SEQ_2_4  =>  CHAN_BOND_SEQ_2_4_BINARY,
          CHAN_BOND_SEQ_2_USE  =>  CHAN_BOND_SEQ_2_USE_BINARY,
          CHAN_BOND_SEQ_LEN  =>  CHAN_BOND_SEQ_LEN_BINARY,
          CHAN_BOND_WAIT  =>  CHAN_BOND_WAIT_BINARY,
          CHBONDDONE  =>  CHBONDDONE_out,
          CHBONDI  =>  CHBONDI_ipd,
          CHBONDO  =>  CHBONDO_out,
          CLK_CORRECT_USE  =>  CLK_CORRECT_USE_BINARY,
          CLK_COR_INSERT_IDLE_FLAG  =>  CLK_COR_INSERT_IDLE_FLAG_BINARY,
          CLK_COR_KEEP_IDLE  =>  CLK_COR_KEEP_IDLE_BINARY,
          CLK_COR_REPEAT_WAIT  =>  CLK_COR_REPEAT_WAIT_BINARY,
          CLK_COR_SEQ_1_1  =>  CLK_COR_SEQ_1_1_BINARY,
          CLK_COR_SEQ_1_2  =>  CLK_COR_SEQ_1_2_BINARY,
          CLK_COR_SEQ_1_3  =>  CLK_COR_SEQ_1_3_BINARY,
          CLK_COR_SEQ_1_4  =>  CLK_COR_SEQ_1_4_BINARY,
          CLK_COR_SEQ_2_1  =>  CLK_COR_SEQ_2_1_BINARY,
          CLK_COR_SEQ_2_2  =>  CLK_COR_SEQ_2_2_BINARY,
          CLK_COR_SEQ_2_3  =>  CLK_COR_SEQ_2_3_BINARY,
          CLK_COR_SEQ_2_4  =>  CLK_COR_SEQ_2_4_BINARY,
          CLK_COR_SEQ_2_USE  =>  CLK_COR_SEQ_2_USE_BINARY,
          CLK_COR_SEQ_LEN  =>  CLK_COR_SEQ_LEN_BINARY,
          COMMA_10B_MASK  =>  COMMA_10B_MASK_BINARY,
          CONFIGENABLE  =>  CONFIGENABLE_ipd,
          CONFIGIN  =>  CONFIGIN_ipd,
          CONFIGOUT  =>  CONFIGOUT_out,
          CRC_END_OF_PKT  =>  CRC_END_OF_PKT_BINARY,
          CRC_FORMAT  =>  CRC_FORMAT_BINARY,
          CRC_START_OF_PKT  =>  CRC_START_OF_PKT_BINARY,
          DEC_MCOMMA_DETECT  =>  DEC_MCOMMA_DETECT_BINARY,
          DEC_PCOMMA_DETECT  =>  DEC_PCOMMA_DETECT_BINARY,
          DEC_VALID_COMMA_ONLY  =>  DEC_VALID_COMMA_ONLY_BINARY,
          ENCHANSYNC  =>  ENCHANSYNC_ipd,
          ENMCOMMAALIGN  =>  ENMCOMMAALIGN_ipd,
          ENPCOMMAALIGN  =>  ENPCOMMAALIGN_ipd,
          GSR  =>  GSR,
          LOOPBACK  =>  LOOPBACK_ipd,
          MCOMMA_10B_VALUE  =>  MCOMMA_10B_VALUE_BINARY,
          MCOMMA_DETECT  =>  MCOMMA_DETECT_BINARY,
          PCOMMA_10B_VALUE  =>  PCOMMA_10B_VALUE_BINARY,
          PCOMMA_DETECT  =>  PCOMMA_DETECT_BINARY,
          POWERDOWN  =>  POWERDOWN_ipd,
          REFCLK  =>  REFCLK_ipd,
          REFCLK2  =>  REFCLK2_ipd,
          REFCLKSEL  =>  REFCLKSEL_ipd,
          REF_CLK_V_SEL  =>  REF_CLK_V_SEL_BINARY,
          RXBUFSTATUS  =>  RXBUFSTATUS_out,
          RXCHARISCOMMA  =>  RXCHARISCOMMA_out,
          RXCHARISK  =>  RXCHARISK_out,
          RXCHECKINGCRC  =>  RXCHECKINGCRC_out,
          RXCLKCORCNT  =>  RXCLKCORCNT_out,
          RXCOMMADET  =>  RXCOMMADET_out,
          RXCRCERR  =>  RXCRCERR_out,
          RXDATA  =>  RXDATA_out,
          RXDISPERR  =>  RXDISPERR_out,
          RXLOSSOFSYNC  =>  RXLOSSOFSYNC_out,
          RXN  =>  RXN_ipd,
          RXNOTINTABLE  =>  RXNOTINTABLE_out,
          RXP  =>  RXP_ipd,
          RXPOLARITY  =>  RXPOLARITY_ipd,
          RXREALIGN  =>  RXREALIGN_out,
          RXRECCLK  =>  RXRECCLK_out,
          RXRESET  =>  RXRESET_ipd,
          RXRUNDISP  =>  RXRUNDISP_out,
          RXUSRCLK  =>  RXUSRCLK_ipd,
          RXUSRCLK2  =>  RXUSRCLK2_ipd,
          RX_BUFFER_USE  =>  RX_BUFFER_USE_BINARY,
          RX_CRC_USE  =>  RX_CRC_USE_BINARY,
          RX_DATA_WIDTH  =>  RX_DATA_WIDTH_BINARY,
          RX_DECODE_USE  =>  RX_DECODE_USE_BINARY,
          RX_LOSS_OF_SYNC_FSM  =>  RX_LOSS_OF_SYNC_FSM_BINARY,
          RX_LOS_INVALID_INCR  =>  RX_LOS_INVALID_INCR_BINARY,
          RX_LOS_THRESHOLD  =>  RX_LOS_THRESHOLD_BINARY,
          SERDES_10B  =>  SERDES_10B_BINARY,
          TERMINATION_IMP  =>  TERMINATION_IMP_BINARY,
          TXBUFERR  =>  TXBUFERR_out,
          TXBYPASS8B10B  =>  TXBYPASS8B10B_ipd,
          TXCHARDISPMODE  =>  TXCHARDISPMODE_ipd,
          TXCHARDISPVAL  =>  TXCHARDISPVAL_ipd,
          TXCHARISK  =>  TXCHARISK_ipd,
          TXDATA  =>  TXDATA_ipd,
          TXFORCECRCERR  =>  TXFORCECRCERR_ipd,
          TXINHIBIT  =>  TXINHIBIT_ipd,
          TXKERR  =>  TXKERR_out,
          TXN  =>  TXN_out,
          TXP  =>  TXP_out,
          TXPOLARITY  =>  TXPOLARITY_ipd,
          TXRESET  =>  TXRESET_ipd,
          TXRUNDISP  =>  TXRUNDISP_out,
          TXUSRCLK  =>  TXUSRCLK_ipd,
          TXUSRCLK2  =>  TXUSRCLK2_ipd,
          TX_BUFFER_USE  =>  TX_BUFFER_USE_BINARY,
          TX_CRC_FORCE_VALUE  =>  TX_CRC_FORCE_VALUE_BINARY,
          TX_CRC_USE  =>  TX_CRC_USE_BINARY,
          TX_DATA_WIDTH  =>  TX_DATA_WIDTH_BINARY,
          TX_DIFF_CTRL  =>  TX_DIFF_CTRL_BINARY,
          TX_PREEMPHASIS  =>  TX_PREEMPHASIS_BINARY

      );

   INIPROC : process
     begin
       case ALIGN_COMMA_MSB is
           when FALSE   =>  ALIGN_COMMA_MSB_BINARY < = '0';
           when TRUE    =>  ALIGN_COMMA_MSB_BINARY < = '1';
           when others  =>  assert FALSE report "Error : ALIGN_COMMA_MSB is neither TRUE nor FALSE." severity warning;
       end case;
       case CHAN_BOND_LIMIT is
           when   1  =>  CHAN_BOND_LIMIT_BINARY < = "00001";
           when   2  =>  CHAN_BOND_LIMIT_BINARY < = "00010";
           when   3  =>  CHAN_BOND_LIMIT_BINARY < = "00011";
           when   4  =>  CHAN_BOND_LIMIT_BINARY < = "00100";
           when   5  =>  CHAN_BOND_LIMIT_BINARY < = "00101";
           when   6  =>  CHAN_BOND_LIMIT_BINARY < = "00110";
           when   7  =>  CHAN_BOND_LIMIT_BINARY < = "00111";
           when   8  =>  CHAN_BOND_LIMIT_BINARY < = "01000";
           when   9  =>  CHAN_BOND_LIMIT_BINARY < = "01001";
           when   10  =>  CHAN_BOND_LIMIT_BINARY < = "01010";
           when   11  =>  CHAN_BOND_LIMIT_BINARY < = "01011";
           when   12  =>  CHAN_BOND_LIMIT_BINARY < = "01100";
           when   13  =>  CHAN_BOND_LIMIT_BINARY < = "01101";
           when   14  =>  CHAN_BOND_LIMIT_BINARY < = "01110";
           when   15  =>  CHAN_BOND_LIMIT_BINARY < = "01111";
           when   16  =>  CHAN_BOND_LIMIT_BINARY < = "10000";
           when   17  =>  CHAN_BOND_LIMIT_BINARY < = "10001";
           when   18  =>  CHAN_BOND_LIMIT_BINARY < = "10010";
           when   19  =>  CHAN_BOND_LIMIT_BINARY < = "10011";
           when   20  =>  CHAN_BOND_LIMIT_BINARY < = "10100";
           when   21  =>  CHAN_BOND_LIMIT_BINARY < = "10101";
           when   22  =>  CHAN_BOND_LIMIT_BINARY < = "10110";
           when   23  =>  CHAN_BOND_LIMIT_BINARY < = "10111";
           when   24  =>  CHAN_BOND_LIMIT_BINARY < = "11000";
           when   25  =>  CHAN_BOND_LIMIT_BINARY < = "11001";
           when   26  =>  CHAN_BOND_LIMIT_BINARY < = "11010";
           when   27  =>  CHAN_BOND_LIMIT_BINARY < = "11011";
           when   28  =>  CHAN_BOND_LIMIT_BINARY < = "11100";
           when   29  =>  CHAN_BOND_LIMIT_BINARY < = "11101";
           when   30  =>  CHAN_BOND_LIMIT_BINARY < = "11110";
           when   31  =>  CHAN_BOND_LIMIT_BINARY < = "11111";
           when others  =>  assert FALSE report "Error : CHAN_BOND_LIMIT is not in range 1...31." severity warning;
       end case;
--     case CHAN_BOND_MODE is
           if((CHAN_BOND_MODE = "OFF") or (CHAN_BOND_MODE = "off")) then
               CHAN_BOND_MODE_BINARY < = "00";
           elsif((CHAN_BOND_MODE = "MASTER") or (CHAN_BOND_MODE = "master")) then
               CHAN_BOND_MODE_BINARY < = "01";
           elsif((CHAN_BOND_MODE = "SLAVE_1_HOP") or (CHAN_BOND_MODE = "slave_1_hop")) then
               CHAN_BOND_MODE_BINARY < = "10";
           elsif((CHAN_BOND_MODE = "SLAVE_2_HOPS") or (CHAN_BOND_MODE = "slave_2_hops")) then
               CHAN_BOND_MODE_BINARY < = "11";
           else
             assert FALSE report "Error : CHAN_BOND_MODE = is not OFF, MASTER, SLAVE_1_HOP, SLAVE_2_HOPS." severity warning;
           end if;
--     end case;
       case CHAN_BOND_OFFSET is
           when   0  =>  CHAN_BOND_OFFSET_BINARY < = "0000";
           when   1  =>  CHAN_BOND_OFFSET_BINARY < = "0001";
           when   2  =>  CHAN_BOND_OFFSET_BINARY < = "0010";
           when   3  =>  CHAN_BOND_OFFSET_BINARY < = "0011";
           when   4  =>  CHAN_BOND_OFFSET_BINARY < = "0100";
           when   5  =>  CHAN_BOND_OFFSET_BINARY < = "0101";
           when   6  =>  CHAN_BOND_OFFSET_BINARY < = "0110";
           when   7  =>  CHAN_BOND_OFFSET_BINARY < = "0111";
           when   8  =>  CHAN_BOND_OFFSET_BINARY < = "1000";
           when   9  =>  CHAN_BOND_OFFSET_BINARY < = "1001";
           when   10  =>  CHAN_BOND_OFFSET_BINARY < = "1010";
           when   11  =>  CHAN_BOND_OFFSET_BINARY < = "1011";
           when   12  =>  CHAN_BOND_OFFSET_BINARY < = "1100";
           when   13  =>  CHAN_BOND_OFFSET_BINARY < = "1101";
           when   14  =>  CHAN_BOND_OFFSET_BINARY < = "1110";
           when   15  =>  CHAN_BOND_OFFSET_BINARY < = "1111";
           when others  =>  assert FALSE report "Error : CHAN_BOND_OFFSET is not in range 0...15." severity warning;
       end case;
       case CHAN_BOND_ONE_SHOT is
           when FALSE   =>  CHAN_BOND_ONE_SHOT_BINARY < = '0';
           when TRUE    =>  CHAN_BOND_ONE_SHOT_BINARY < = '1';
           when others  =>  assert FALSE report "Error : CHAN_BOND_ONE_SHOT is neither TRUE nor FALSE." severity warning;
       end case;
       case CHAN_BOND_SEQ_2_USE is
           when FALSE   =>  CHAN_BOND_SEQ_2_USE_BINARY < = '0';
           when TRUE    =>  CHAN_BOND_SEQ_2_USE_BINARY < = '1';
           when others  =>  assert FALSE report "Error : CHAN_BOND_SEQ_2_USE is neither TRUE nor FALSE." severity warning;
       end case;
       case CHAN_BOND_SEQ_LEN is
           when   1  =>  CHAN_BOND_SEQ_LEN_BINARY < = "01";
           when   2  =>  CHAN_BOND_SEQ_LEN_BINARY < = "10";
           when   3  =>  CHAN_BOND_SEQ_LEN_BINARY < = "11";
           when   4  =>  CHAN_BOND_SEQ_LEN_BINARY < = "00";
           when others  =>  assert FALSE report "Error : CHAN_BOND_SEQ_LEN is not in range 1...4." severity warning;
       end case;
       case CHAN_BOND_WAIT is
           when   1  =>  CHAN_BOND_WAIT_BINARY < = "0001";
           when   2  =>  CHAN_BOND_WAIT_BINARY < = "0010";
           when   3  =>  CHAN_BOND_WAIT_BINARY < = "0011";
           when   4  =>  CHAN_BOND_WAIT_BINARY < = "0100";
           when   5  =>  CHAN_BOND_WAIT_BINARY < = "0101";
           when   6  =>  CHAN_BOND_WAIT_BINARY < = "0110";
           when   7  =>  CHAN_BOND_WAIT_BINARY < = "0111";
           when   8  =>  CHAN_BOND_WAIT_BINARY < = "1000";
           when   9  =>  CHAN_BOND_WAIT_BINARY < = "1001";
           when   10  =>  CHAN_BOND_WAIT_BINARY < = "1010";
           when   11  =>  CHAN_BOND_WAIT_BINARY < = "1011";
           when   12  =>  CHAN_BOND_WAIT_BINARY < = "1100";
           when   13  =>  CHAN_BOND_WAIT_BINARY < = "1101";
           when   14  =>  CHAN_BOND_WAIT_BINARY < = "1110";
           when   15  =>  CHAN_BOND_WAIT_BINARY < = "1111";
           when others  =>  assert FALSE report "Error : CHAN_BOND_WAIT is not in range 1...15." severity warning;
       end case;
       case CLK_COR_INSERT_IDLE_FLAG is
           when FALSE   =>  CLK_COR_INSERT_IDLE_FLAG_BINARY < = '0';
           when TRUE    =>  CLK_COR_INSERT_IDLE_FLAG_BINARY < = '1';
           when others  =>  assert FALSE report "Error : CLK_COR_INSERT_IDLE_FLAG is neither TRUE nor FALSE." severity warning;
       end case;
       case CLK_COR_KEEP_IDLE is
           when FALSE   =>  CLK_COR_KEEP_IDLE_BINARY < = '0';
           when TRUE    =>  CLK_COR_KEEP_IDLE_BINARY < = '1';
           when others  =>  assert FALSE report "Error : CLK_COR_KEEP_IDLE is neither TRUE nor FALSE." severity warning;
       end case;
       case CLK_COR_REPEAT_WAIT is
           when   0  =>  CLK_COR_REPEAT_WAIT_BINARY < = "00000";
           when   1  =>  CLK_COR_REPEAT_WAIT_BINARY < = "00001";
           when   2  =>  CLK_COR_REPEAT_WAIT_BINARY < = "00010";
           when   3  =>  CLK_COR_REPEAT_WAIT_BINARY < = "00011";
           when   4  =>  CLK_COR_REPEAT_WAIT_BINARY < = "00100";
           when   5  =>  CLK_COR_REPEAT_WAIT_BINARY < = "00101";
           when   6  =>  CLK_COR_REPEAT_WAIT_BINARY < = "00110";
           when   7  =>  CLK_COR_REPEAT_WAIT_BINARY < = "00111";
           when   8  =>  CLK_COR_REPEAT_WAIT_BINARY < = "01000";
           when   9  =>  CLK_COR_REPEAT_WAIT_BINARY < = "01001";
           when   10  =>  CLK_COR_REPEAT_WAIT_BINARY < = "01010";
           when   11  =>  CLK_COR_REPEAT_WAIT_BINARY < = "01011";
           when   12  =>  CLK_COR_REPEAT_WAIT_BINARY < = "01100";
           when   13  =>  CLK_COR_REPEAT_WAIT_BINARY < = "01101";
           when   14  =>  CLK_COR_REPEAT_WAIT_BINARY < = "01110";
           when   15  =>  CLK_COR_REPEAT_WAIT_BINARY < = "01111";
           when   16  =>  CLK_COR_REPEAT_WAIT_BINARY < = "10000";
           when   17  =>  CLK_COR_REPEAT_WAIT_BINARY < = "10001";
           when   18  =>  CLK_COR_REPEAT_WAIT_BINARY < = "10010";
           when   19  =>  CLK_COR_REPEAT_WAIT_BINARY < = "10011";
           when   20  =>  CLK_COR_REPEAT_WAIT_BINARY < = "10100";
           when   21  =>  CLK_COR_REPEAT_WAIT_BINARY < = "10101";
           when   22  =>  CLK_COR_REPEAT_WAIT_BINARY < = "10110";
           when   23  =>  CLK_COR_REPEAT_WAIT_BINARY < = "10111";
           when   24  =>  CLK_COR_REPEAT_WAIT_BINARY < = "11000";
           when   25  =>  CLK_COR_REPEAT_WAIT_BINARY < = "11001";
           when   26  =>  CLK_COR_REPEAT_WAIT_BINARY < = "11010";
           when   27  =>  CLK_COR_REPEAT_WAIT_BINARY < = "11011";
           when   28  =>  CLK_COR_REPEAT_WAIT_BINARY < = "11100";
           when   29  =>  CLK_COR_REPEAT_WAIT_BINARY < = "11101";
           when   30  =>  CLK_COR_REPEAT_WAIT_BINARY < = "11110";
           when   31  =>  CLK_COR_REPEAT_WAIT_BINARY < = "11111";
           when others  =>  assert FALSE report "Error : CLK_COR_REPEAT_WAIT is not in range 0...31." severity warning;
       end case;
       case CLK_COR_SEQ_2_USE is
           when FALSE   =>  CLK_COR_SEQ_2_USE_BINARY < = '0';
           when TRUE    =>  CLK_COR_SEQ_2_USE_BINARY < = '1';
           when others  =>  assert FALSE report "Error : CLK_COR_SEQ_2_USE is neither TRUE nor FALSE." severity warning;
       end case;
       case CLK_COR_SEQ_LEN is
           when   1  =>  CLK_COR_SEQ_LEN_BINARY < = "01";
           when   2  =>  CLK_COR_SEQ_LEN_BINARY < = "10";
           when   3  =>  CLK_COR_SEQ_LEN_BINARY < = "11";
           when   4  =>  CLK_COR_SEQ_LEN_BINARY < = "00";
           when others  =>  assert FALSE report "Error : CLK_COR_SEQ_LEN is not in range 1...4." severity warning;
       end case;
       case CLK_CORRECT_USE is
           when FALSE   =>  CLK_CORRECT_USE_BINARY < = '0';
           when TRUE    =>  CLK_CORRECT_USE_BINARY < = '1';
           when others  =>  assert FALSE report "Error : CLK_CORRECT_USE is neither TRUE nor FALSE." severity warning;
       end case;
--     case CRC_END_OF_PKT is
           if((CRC_END_OF_PKT = "K28_0") or (CRC_END_OF_PKT = "k28_0")) then
               CRC_END_OF_PKT_BINARY < = "00011100";
           elsif((CRC_END_OF_PKT = "K28_1") or (CRC_END_OF_PKT = "k28_1")) then
               CRC_END_OF_PKT_BINARY < = "00111100";
           elsif((CRC_END_OF_PKT = "K28_2") or (CRC_END_OF_PKT = "k28_2")) then
               CRC_END_OF_PKT_BINARY < = "01011100";
           elsif((CRC_END_OF_PKT = "K28_3") or (CRC_END_OF_PKT = "k28_3")) then
               CRC_END_OF_PKT_BINARY < = "01111100";
           elsif((CRC_END_OF_PKT = "K28_4") or (CRC_END_OF_PKT = "k28_4")) then
               CRC_END_OF_PKT_BINARY < = "10011100";
           elsif((CRC_END_OF_PKT = "K28_5") or (CRC_END_OF_PKT = "k28_5")) then
               CRC_END_OF_PKT_BINARY < = "10111100";
           elsif((CRC_END_OF_PKT = "K28_6") or (CRC_END_OF_PKT = "k28_6")) then
               CRC_END_OF_PKT_BINARY < = "11011100";
           elsif((CRC_END_OF_PKT = "K28_7") or (CRC_END_OF_PKT = "k28_7")) then
               CRC_END_OF_PKT_BINARY < = "11111100";
           elsif((CRC_END_OF_PKT = "K23_7") or (CRC_END_OF_PKT = "k23_7")) then
               CRC_END_OF_PKT_BINARY < = "11110111";
           elsif((CRC_END_OF_PKT = "K27_7") or (CRC_END_OF_PKT = "k27_7")) then
               CRC_END_OF_PKT_BINARY < = "11111011";
           elsif((CRC_END_OF_PKT = "K29_7") or (CRC_END_OF_PKT = "k29_7")) then
               CRC_END_OF_PKT_BINARY < = "11111101";
           elsif((CRC_END_OF_PKT = "K30_7") or (CRC_END_OF_PKT = "k30_7")) then
               CRC_END_OF_PKT_BINARY < = "11111110";
           else
             assert FALSE report "Error : CRC_END_OF_PKT = is not K28_0, K28_1, K28_2, K28_3, K28_4, K28_5, K28_6, K28_7, K23_7, K27_7, K29_7, K30_7." severity warning;
           end if;
--     end case;
--     case CRC_FORMAT is
           if((CRC_FORMAT = "USER_MODE") or (CRC_FORMAT = "user_mode")) then
               CRC_FORMAT_BINARY < = "00";
           elsif((CRC_FORMAT = "ETHERNET") or (CRC_FORMAT = "ethernet")) then
               CRC_FORMAT_BINARY < = "01";
           elsif((CRC_FORMAT = "INFINIBAND") or (CRC_FORMAT = "infiniband")) then
               CRC_FORMAT_BINARY < = "10";
           elsif((CRC_FORMAT = "FIBRE_CHAN") or (CRC_FORMAT = "fibre_chan")) then
               CRC_FORMAT_BINARY < = "11";
           else
             assert FALSE report "Error : CRC_FORMAT = is not USER_MODE, ETHERNET, INFINIBAND, FIBRE_CHAN." severity warning;
           end if;
--     end case;
--     case CRC_START_OF_PKT is
           if((CRC_START_OF_PKT = "K28_0") or (CRC_START_OF_PKT = "k28_0")) then
               CRC_START_OF_PKT_BINARY < = "00011100";
           elsif((CRC_START_OF_PKT = "K28_1") or (CRC_START_OF_PKT = "k28_1")) then
               CRC_START_OF_PKT_BINARY < = "00111100";
           elsif((CRC_START_OF_PKT = "K28_2") or (CRC_START_OF_PKT = "k28_2")) then
               CRC_START_OF_PKT_BINARY < = "01011100";
           elsif((CRC_START_OF_PKT = "K28_3") or (CRC_START_OF_PKT = "k28_3")) then
               CRC_START_OF_PKT_BINARY < = "01111100";
           elsif((CRC_START_OF_PKT = "K28_4") or (CRC_START_OF_PKT = "k28_4")) then
               CRC_START_OF_PKT_BINARY < = "10011100";
           elsif((CRC_START_OF_PKT = "K28_5") or (CRC_START_OF_PKT = "k28_5")) then
               CRC_START_OF_PKT_BINARY < = "10111100";
           elsif((CRC_START_OF_PKT = "K28_6") or (CRC_START_OF_PKT = "k28_6")) then
               CRC_START_OF_PKT_BINARY < = "11011100";
           elsif((CRC_START_OF_PKT = "K28_7") or (CRC_START_OF_PKT = "k28_7")) then
               CRC_START_OF_PKT_BINARY < = "11111100";
           elsif((CRC_START_OF_PKT = "K23_7") or (CRC_START_OF_PKT = "k23_7")) then
               CRC_START_OF_PKT_BINARY < = "11110111";
           elsif((CRC_START_OF_PKT = "K27_7") or (CRC_START_OF_PKT = "k27_7")) then
               CRC_START_OF_PKT_BINARY < = "11111011";
           elsif((CRC_START_OF_PKT = "K29_7") or (CRC_START_OF_PKT = "k29_7")) then
               CRC_START_OF_PKT_BINARY < = "11111101";
           elsif((CRC_START_OF_PKT = "K30_7") or (CRC_START_OF_PKT = "k30_7")) then
               CRC_START_OF_PKT_BINARY < = "11111110";
           else
             assert FALSE report "Error : CRC_START_OF_PKT = is not K28_0, K28_1, K28_2, K28_3, K28_4, K28_5, K28_6, K28_7, K23_7, K27_7, K29_7, K30_7." severity warning;
           end if;
--     end case;
       case DEC_MCOMMA_DETECT is
           when FALSE   =>  DEC_MCOMMA_DETECT_BINARY < = '0';
           when TRUE    =>  DEC_MCOMMA_DETECT_BINARY < = '1';
           when others  =>  assert FALSE report "Error : DEC_MCOMMA_DETECT is neither TRUE nor FALSE." severity warning;
       end case;
       case DEC_PCOMMA_DETECT is
           when FALSE   =>  DEC_PCOMMA_DETECT_BINARY < = '0';
           when TRUE    =>  DEC_PCOMMA_DETECT_BINARY < = '1';
           when others  =>  assert FALSE report "Error : DEC_PCOMMA_DETECT is neither TRUE nor FALSE." severity warning;
       end case;
       case DEC_VALID_COMMA_ONLY is
           when FALSE   =>  DEC_VALID_COMMA_ONLY_BINARY < = '0';
           when TRUE    =>  DEC_VALID_COMMA_ONLY_BINARY < = '1';
           when others  =>  assert FALSE report "Error : DEC_VALID_COMMA_ONLY is neither TRUE nor FALSE." severity warning;
       end case;
       case MCOMMA_DETECT is
           when FALSE   =>  MCOMMA_DETECT_BINARY < = '0';
           when TRUE    =>  MCOMMA_DETECT_BINARY < = '1';
           when others  =>  assert FALSE report "Error : MCOMMA_DETECT is neither TRUE nor FALSE." severity warning;
       end case;
       case PCOMMA_DETECT is
           when FALSE   =>  PCOMMA_DETECT_BINARY < = '0';
           when TRUE    =>  PCOMMA_DETECT_BINARY < = '1';
           when others  =>  assert FALSE report "Error : PCOMMA_DETECT is neither TRUE nor FALSE." severity warning;
       end case;
       case REF_CLK_V_SEL is
           when   0  =>  REF_CLK_V_SEL_BINARY < = '0';
           when   1  =>  REF_CLK_V_SEL_BINARY < = '1';
           when others  =>  assert FALSE report "Error : REF_CLK_V_SEL is not in 0, 1." severity warning;
       end case;
       case RX_BUFFER_USE is
           when FALSE   =>  RX_BUFFER_USE_BINARY < = '0';
           when TRUE    =>  RX_BUFFER_USE_BINARY < = '1';
           when others  =>  assert FALSE report "Error : RX_BUFFER_USE is neither TRUE nor FALSE." severity warning;
       end case;
       case RX_CRC_USE is
           when FALSE   =>  RX_CRC_USE_BINARY < = '0';
           when TRUE    =>  RX_CRC_USE_BINARY < = '1';
           when others  =>  assert FALSE report "Error : RX_CRC_USE is neither TRUE nor FALSE." severity warning;
       end case;
       case RX_DATA_WIDTH is
           when   1  =>  RX_DATA_WIDTH_BINARY < = "01";
           when   2  =>  RX_DATA_WIDTH_BINARY < = "10";
           when   4  =>  RX_DATA_WIDTH_BINARY < = "00";
           when others  =>  assert FALSE report "Error : RX_DATA_WIDTH is not in 1, 2, 4." severity warning;
       end case;
       case RX_DECODE_USE is
           when FALSE   =>  RX_DECODE_USE_BINARY < = '0';
           when TRUE    =>  RX_DECODE_USE_BINARY < = '1';
           when others  =>  assert FALSE report "Error : RX_DECODE_USE is neither TRUE nor FALSE." severity warning;
       end case;
       case RX_LOS_INVALID_INCR is
           when   1  =>  RX_LOS_INVALID_INCR_BINARY < = "000";
           when   2  =>  RX_LOS_INVALID_INCR_BINARY < = "001";
           when   4  =>  RX_LOS_INVALID_INCR_BINARY < = "010";
           when   8  =>  RX_LOS_INVALID_INCR_BINARY < = "011";
           when   16  =>  RX_LOS_INVALID_INCR_BINARY < = "100";
           when   32  =>  RX_LOS_INVALID_INCR_BINARY < = "101";
           when   64  =>  RX_LOS_INVALID_INCR_BINARY < = "110";
           when   128  =>  RX_LOS_INVALID_INCR_BINARY < = "111";
           when others  =>  assert FALSE report "Error : RX_LOS_INVALID_INCR is not in 1, 2, 4, 8, 16, 32, 64, 128." severity warning;
       end case;
       case RX_LOS_THRESHOLD is
           when   4  =>  RX_LOS_THRESHOLD_BINARY < = "000";
           when   8  =>  RX_LOS_THRESHOLD_BINARY < = "001";
           when   16  =>  RX_LOS_THRESHOLD_BINARY < = "010";
           when   32  =>  RX_LOS_THRESHOLD_BINARY < = "011";
           when   64  =>  RX_LOS_THRESHOLD_BINARY < = "100";
           when   128  =>  RX_LOS_THRESHOLD_BINARY < = "101";
           when   256  =>  RX_LOS_THRESHOLD_BINARY < = "110";
           when   512  =>  RX_LOS_THRESHOLD_BINARY < = "111";
           when others  =>  assert FALSE report "Error : RX_LOS_THRESHOLD is not in 4, 8, 16, 32, 64, 128, 256, 512." severity warning;
       end case;
       case RX_LOSS_OF_SYNC_FSM is
           when FALSE   =>  RX_LOSS_OF_SYNC_FSM_BINARY < = '0';
           when TRUE    =>  RX_LOSS_OF_SYNC_FSM_BINARY < = '1';
           when others  =>  assert FALSE report "Error : RX_LOSS_OF_SYNC_FSM is neither TRUE nor FALSE." severity warning;
       end case;
       case SERDES_10B is
           when FALSE   =>  SERDES_10B_BINARY < = '0';
           when TRUE    =>  SERDES_10B_BINARY < = '1';
           when others  =>  assert FALSE report "Error : SERDES_10B is neither TRUE nor FALSE." severity warning;
       end case;
       case TERMINATION_IMP is
           when   50  =>  TERMINATION_IMP_BINARY < = '0';
           when   75  =>  TERMINATION_IMP_BINARY < = '1';
           when others  =>  assert FALSE report "Error : TERMINATION_IMP is not in 50, 75." severity warning;
       end case;
       case TX_BUFFER_USE is
           when FALSE   =>  TX_BUFFER_USE_BINARY < = '0';
           when TRUE    =>  TX_BUFFER_USE_BINARY < = '1';
           when others  =>  assert FALSE report "Error : TX_BUFFER_USE is neither TRUE nor FALSE." severity warning;
       end case;
       case TX_CRC_USE is
           when FALSE   =>  TX_CRC_USE_BINARY < = '0';
           when TRUE    =>  TX_CRC_USE_BINARY < = '1';
           when others  =>  assert FALSE report "Error : TX_CRC_USE is neither TRUE nor FALSE." severity warning;
       end case;
       case TX_DATA_WIDTH is
           when   1  =>  TX_DATA_WIDTH_BINARY < = "01";
           when   2  =>  TX_DATA_WIDTH_BINARY < = "10";
           when   4  =>  TX_DATA_WIDTH_BINARY < = "00";
           when others  =>  assert FALSE report "Error : TX_DATA_WIDTH is not in 1, 2, 4." severity warning;
       end case;
       case TX_DIFF_CTRL is
           when   400  =>  TX_DIFF_CTRL_BINARY < = "010";
           when   500  =>  TX_DIFF_CTRL_BINARY < = "000";
           when   600  =>  TX_DIFF_CTRL_BINARY < = "001";
           when   700  =>  TX_DIFF_CTRL_BINARY < = "011";
           when   800  =>  TX_DIFF_CTRL_BINARY < = "110";
           when others  =>  assert FALSE report "Error : TX_DIFF_CTRL is not in 400, 500, 600, 700, 800." severity warning;
       end case;
       case TX_PREEMPHASIS is
           when   0  =>  TX_PREEMPHASIS_BINARY < = "00";
           when   1  =>  TX_PREEMPHASIS_BINARY < = "01";
           when   2  =>  TX_PREEMPHASIS_BINARY < = "10";
           when   3  =>  TX_PREEMPHASIS_BINARY < = "11";
           when others  =>  assert FALSE report "Error : TX_PREEMPHASIS is not in 0, 1, 2, 3." severity warning;
       end case;
     wait;
   end process INIPROC;

   TIMING : process

--  Pin timing violations (clock input pins)

--  Pin Timing Violations (all input pins)

--  Output Pin glitch declaration
     variable  CHBONDDONE_GlitchData : VitalGlitchDataType;
     variable  CHBONDO0_GlitchData : VitalGlitchDataType;
     variable  CHBONDO1_GlitchData : VitalGlitchDataType;
     variable  CHBONDO2_GlitchData : VitalGlitchDataType;
     variable  CHBONDO3_GlitchData : VitalGlitchDataType;
     variable  CONFIGOUT_GlitchData : VitalGlitchDataType;
     variable  RXBUFSTATUS0_GlitchData : VitalGlitchDataType;
     variable  RXBUFSTATUS1_GlitchData : VitalGlitchDataType;
     variable  RXCHARISCOMMA0_GlitchData : VitalGlitchDataType;
     variable  RXCHARISCOMMA1_GlitchData : VitalGlitchDataType;
     variable  RXCHARISCOMMA2_GlitchData : VitalGlitchDataType;
     variable  RXCHARISCOMMA3_GlitchData : VitalGlitchDataType;
     variable  RXCHARISK0_GlitchData : VitalGlitchDataType;
     variable  RXCHARISK1_GlitchData : VitalGlitchDataType;
     variable  RXCHARISK2_GlitchData : VitalGlitchDataType;
     variable  RXCHARISK3_GlitchData : VitalGlitchDataType;
     variable  RXCHECKINGCRC_GlitchData : VitalGlitchDataType;
     variable  RXCLKCORCNT0_GlitchData : VitalGlitchDataType;
     variable  RXCLKCORCNT1_GlitchData : VitalGlitchDataType;
     variable  RXCLKCORCNT2_GlitchData : VitalGlitchDataType;
     variable  RXCOMMADET_GlitchData : VitalGlitchDataType;
     variable  RXCRCERR_GlitchData : VitalGlitchDataType;
     variable  RXDATA0_GlitchData : VitalGlitchDataType;
     variable  RXDATA1_GlitchData : VitalGlitchDataType;
     variable  RXDATA2_GlitchData : VitalGlitchDataType;
     variable  RXDATA3_GlitchData : VitalGlitchDataType;
     variable  RXDATA4_GlitchData : VitalGlitchDataType;
     variable  RXDATA5_GlitchData : VitalGlitchDataType;
     variable  RXDATA6_GlitchData : VitalGlitchDataType;
     variable  RXDATA7_GlitchData : VitalGlitchDataType;
     variable  RXDATA8_GlitchData : VitalGlitchDataType;
     variable  RXDATA9_GlitchData : VitalGlitchDataType;
     variable  RXDATA10_GlitchData : VitalGlitchDataType;
     variable  RXDATA11_GlitchData : VitalGlitchDataType;
     variable  RXDATA12_GlitchData : VitalGlitchDataType;
     variable  RXDATA13_GlitchData : VitalGlitchDataType;
     variable  RXDATA14_GlitchData : VitalGlitchDataType;
     variable  RXDATA15_GlitchData : VitalGlitchDataType;
     variable  RXDATA16_GlitchData : VitalGlitchDataType;
     variable  RXDATA17_GlitchData : VitalGlitchDataType;
     variable  RXDATA18_GlitchData : VitalGlitchDataType;
     variable  RXDATA19_GlitchData : VitalGlitchDataType;
     variable  RXDATA20_GlitchData : VitalGlitchDataType;
     variable  RXDATA21_GlitchData : VitalGlitchDataType;
     variable  RXDATA22_GlitchData : VitalGlitchDataType;
     variable  RXDATA23_GlitchData : VitalGlitchDataType;
     variable  RXDATA24_GlitchData : VitalGlitchDataType;
     variable  RXDATA25_GlitchData : VitalGlitchDataType;
     variable  RXDATA26_GlitchData : VitalGlitchDataType;
     variable  RXDATA27_GlitchData : VitalGlitchDataType;
     variable  RXDATA28_GlitchData : VitalGlitchDataType;
     variable  RXDATA29_GlitchData : VitalGlitchDataType;
     variable  RXDATA30_GlitchData : VitalGlitchDataType;
     variable  RXDATA31_GlitchData : VitalGlitchDataType;
     variable  RXDISPERR0_GlitchData : VitalGlitchDataType;
     variable  RXDISPERR1_GlitchData : VitalGlitchDataType;
     variable  RXDISPERR2_GlitchData : VitalGlitchDataType;
     variable  RXDISPERR3_GlitchData : VitalGlitchDataType;
     variable  RXLOSSOFSYNC0_GlitchData : VitalGlitchDataType;
     variable  RXLOSSOFSYNC1_GlitchData : VitalGlitchDataType;
     variable  RXNOTINTABLE0_GlitchData : VitalGlitchDataType;
     variable  RXNOTINTABLE1_GlitchData : VitalGlitchDataType;
     variable  RXNOTINTABLE2_GlitchData : VitalGlitchDataType;
     variable  RXNOTINTABLE3_GlitchData : VitalGlitchDataType;
     variable  RXREALIGN_GlitchData : VitalGlitchDataType;
--     variable  RXRECCLK_GlitchData : VitalGlitchDataType;
     variable  RXRUNDISP0_GlitchData : VitalGlitchDataType;
     variable  RXRUNDISP1_GlitchData : VitalGlitchDataType;
     variable  RXRUNDISP2_GlitchData : VitalGlitchDataType;
     variable  RXRUNDISP3_GlitchData : VitalGlitchDataType;
     variable  TXBUFERR_GlitchData : VitalGlitchDataType;
     variable  TXKERR0_GlitchData : VitalGlitchDataType;
     variable  TXKERR1_GlitchData : VitalGlitchDataType;
     variable  TXKERR2_GlitchData : VitalGlitchDataType;
     variable  TXKERR3_GlitchData : VitalGlitchDataType;
--     variable  TXN_GlitchData : VitalGlitchDataType;
--     variable  TXP_GlitchData : VitalGlitchDataType;
     variable  TXRUNDISP0_GlitchData : VitalGlitchDataType;
     variable  TXRUNDISP1_GlitchData : VitalGlitchDataType;
     variable  TXRUNDISP2_GlitchData : VitalGlitchDataType;
     variable  TXRUNDISP3_GlitchData : VitalGlitchDataType;
begin

--  Setup/Hold Check Violations (all input pins)


-- End of (TimingChecksOn)

--  Output-to-Clock path delay
     VitalPathDelay01
       (
         OutSignal     => CHBONDDONE,
         GlitchData    => CHBONDDONE_GlitchData,
         OutSignalName => "CHBONDDONE",
         OutTemp       => CHBONDDONE_OUT,
         Paths         => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => CHBONDO(0),
         GlitchData    => CHBONDO0_GlitchData,
         OutSignalName => "CHBONDO(0)",
         OutTemp       => CHBONDO_OUT(0),
         Paths         => (0 => (RXUSRCLK_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => CHBONDO(1),
         GlitchData    => CHBONDO1_GlitchData,
         OutSignalName => "CHBONDO(1)",
         OutTemp       => CHBONDO_OUT(1),
         Paths         => (0 => (RXUSRCLK_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => CHBONDO(2),
         GlitchData    => CHBONDO2_GlitchData,
         OutSignalName => "CHBONDO(2)",
         OutTemp       => CHBONDO_OUT(2),
         Paths         => (0 => (RXUSRCLK_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => CHBONDO(3),
         GlitchData    => CHBONDO3_GlitchData,
         OutSignalName => "CHBONDO(3)",
         OutTemp       => CHBONDO_OUT(3),
         Paths         => (0 => (RXUSRCLK_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => CONFIGOUT,
         GlitchData    => CONFIGOUT_GlitchData,
         OutSignalName => "CONFIGOUT",
         OutTemp       => CONFIGOUT_OUT,
         Paths         => (0 => (TXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => RXBUFSTATUS(0),
         GlitchData    => RXBUFSTATUS0_GlitchData,
         OutSignalName => "RXBUFSTATUS(0)",
         OutTemp       => RXBUFSTATUS_OUT(0),
         Paths         => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => RXBUFSTATUS(1),
         GlitchData    => RXBUFSTATUS1_GlitchData,
         OutSignalName => "RXBUFSTATUS(1)",
         OutTemp       => RXBUFSTATUS_OUT(1),
         Paths         => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => RXCHARISCOMMA(0),
         GlitchData    => RXCHARISCOMMA0_GlitchData,
         OutSignalName => "RXCHARISCOMMA(0)",
         OutTemp       => RXCHARISCOMMA_OUT(0),
         Paths         => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => RXCHARISCOMMA(1),
         GlitchData    => RXCHARISCOMMA1_GlitchData,
         OutSignalName => "RXCHARISCOMMA(1)",
         OutTemp       => RXCHARISCOMMA_OUT(1),
         Paths         => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => RXCHARISCOMMA(2),
         GlitchData    => RXCHARISCOMMA2_GlitchData,
         OutSignalName => "RXCHARISCOMMA(2)",
         OutTemp       => RXCHARISCOMMA_OUT(2),
         Paths         => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => RXCHARISCOMMA(3),
         GlitchData    => RXCHARISCOMMA3_GlitchData,
         OutSignalName => "RXCHARISCOMMA(3)",
         OutTemp       => RXCHARISCOMMA_OUT(3),
         Paths         => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => RXCHARISK(0),
         GlitchData    => RXCHARISK0_GlitchData,
         OutSignalName => "RXCHARISK(0)",
         OutTemp       => RXCHARISK_OUT(0),
         Paths         => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => RXCHARISK(1),
         GlitchData    => RXCHARISK1_GlitchData,
         OutSignalName => "RXCHARISK(1)",
         OutTemp       => RXCHARISK_OUT(1),
         Paths         => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => RXCHARISK(2),
         GlitchData    => RXCHARISK2_GlitchData,
         OutSignalName => "RXCHARISK(2)",
         OutTemp       => RXCHARISK_OUT(2),
         Paths         => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => RXCHARISK(3),
         GlitchData    => RXCHARISK3_GlitchData,
         OutSignalName => "RXCHARISK(3)",
         OutTemp       => RXCHARISK_OUT(3),
         Paths         => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => RXCHECKINGCRC,
         GlitchData    => RXCHECKINGCRC_GlitchData,
         OutSignalName => "RXCHECKINGCRC",
         OutTemp       => RXCHECKINGCRC_OUT,
         Paths         => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => RXCLKCORCNT(0),
         GlitchData    => RXCLKCORCNT0_GlitchData,
         OutSignalName => "RXCLKCORCNT(0)",
         OutTemp       => RXCLKCORCNT_OUT(0),
         Paths         => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => RXCLKCORCNT(1),
         GlitchData    => RXCLKCORCNT1_GlitchData,
         OutSignalName => "RXCLKCORCNT(1)",
         OutTemp       => RXCLKCORCNT_OUT(1),
         Paths         => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => RXCLKCORCNT(2),
         GlitchData    => RXCLKCORCNT2_GlitchData,
         OutSignalName => "RXCLKCORCNT(2)",
         OutTemp       => RXCLKCORCNT_OUT(2),
         Paths         => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => RXCOMMADET,
         GlitchData    => RXCOMMADET_GlitchData,
         OutSignalName => "RXCOMMADET",
         OutTemp       => RXCOMMADET_OUT,
         Paths         => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => RXCRCERR,
         GlitchData    => RXCRCERR_GlitchData,
         OutSignalName => "RXCRCERR",
         OutTemp       => RXCRCERR_OUT,
         Paths         => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => RXDATA(0),
         GlitchData    => RXDATA0_GlitchData,
         OutSignalName => "RXDATA(0)",
         OutTemp       => RXDATA_OUT(0),
         Paths         => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => RXDATA(1),
         GlitchData    => RXDATA1_GlitchData,
         OutSignalName => "RXDATA(1)",
         OutTemp       => RXDATA_OUT(1),
         Paths         => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => RXDATA(2),
         GlitchData    => RXDATA2_GlitchData,
         OutSignalName => "RXDATA(2)",
         OutTemp       => RXDATA_OUT(2),
         Paths         => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => RXDATA(3),
         GlitchData    => RXDATA3_GlitchData,
         OutSignalName => "RXDATA(3)",
         OutTemp       => RXDATA_OUT(3),
         Paths         => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => RXDATA(4),
         GlitchData    => RXDATA4_GlitchData,
         OutSignalName => "RXDATA(4)",
         OutTemp       => RXDATA_OUT(4),
         Paths         => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => RXDATA(5),
         GlitchData    => RXDATA5_GlitchData,
         OutSignalName => "RXDATA(5)",
         OutTemp       => RXDATA_OUT(5),
         Paths         => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => RXDATA(6),
         GlitchData    => RXDATA6_GlitchData,
         OutSignalName => "RXDATA(6)",
         OutTemp       => RXDATA_OUT(6),
         Paths         => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => RXDATA(7),
         GlitchData    => RXDATA7_GlitchData,
         OutSignalName => "RXDATA(7)",
         OutTemp       => RXDATA_OUT(7),
         Paths         => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => RXDATA(8),
         GlitchData    => RXDATA8_GlitchData,
         OutSignalName => "RXDATA(8)",
         OutTemp       => RXDATA_OUT(8),
         Paths         => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => RXDATA(9),
         GlitchData    => RXDATA9_GlitchData,
         OutSignalName => "RXDATA(9)",
         OutTemp       => RXDATA_OUT(9),
         Paths         => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => RXDATA(10),
         GlitchData    => RXDATA10_GlitchData,
         OutSignalName => "RXDATA(10)",
         OutTemp       => RXDATA_OUT(10),
         Paths         => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => RXDATA(11),
         GlitchData    => RXDATA11_GlitchData,
         OutSignalName => "RXDATA(11)",
         OutTemp       => RXDATA_OUT(11),
         Paths         => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => RXDATA(12),
         GlitchData    => RXDATA12_GlitchData,
         OutSignalName => "RXDATA(12)",
         OutTemp       => RXDATA_OUT(12),
         Paths         => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => RXDATA(13),
         GlitchData    => RXDATA13_GlitchData,
         OutSignalName => "RXDATA(13)",
         OutTemp       => RXDATA_OUT(13),
         Paths         => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => RXDATA(14),
         GlitchData    => RXDATA14_GlitchData,
         OutSignalName => "RXDATA(14)",
         OutTemp       => RXDATA_OUT(14),
         Paths         => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => RXDATA(15),
         GlitchData    => RXDATA15_GlitchData,
         OutSignalName => "RXDATA(15)",
         OutTemp       => RXDATA_OUT(15),
         Paths         => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => RXDATA(16),
         GlitchData    => RXDATA16_GlitchData,
         OutSignalName => "RXDATA(16)",
         OutTemp       => RXDATA_OUT(16),
         Paths         => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => RXDATA(17),
         GlitchData    => RXDATA17_GlitchData,
         OutSignalName => "RXDATA(17)",
         OutTemp       => RXDATA_OUT(17),
         Paths         => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => RXDATA(18),
         GlitchData    => RXDATA18_GlitchData,
         OutSignalName => "RXDATA(18)",
         OutTemp       => RXDATA_OUT(18),
         Paths         => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => RXDATA(19),
         GlitchData    => RXDATA19_GlitchData,
         OutSignalName => "RXDATA(19)",
         OutTemp       => RXDATA_OUT(19),
         Paths         => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => RXDATA(20),
         GlitchData    => RXDATA20_GlitchData,
         OutSignalName => "RXDATA(20)",
         OutTemp       => RXDATA_OUT(20),
         Paths         => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => RXDATA(21),
         GlitchData    => RXDATA21_GlitchData,
         OutSignalName => "RXDATA(21)",
         OutTemp       => RXDATA_OUT(21),
         Paths         => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => RXDATA(22),
         GlitchData    => RXDATA22_GlitchData,
         OutSignalName => "RXDATA(22)",
         OutTemp       => RXDATA_OUT(22),
         Paths         => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => RXDATA(23),
         GlitchData    => RXDATA23_GlitchData,
         OutSignalName => "RXDATA(23)",
         OutTemp       => RXDATA_OUT(23),
         Paths         => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => RXDATA(24),
         GlitchData    => RXDATA24_GlitchData,
         OutSignalName => "RXDATA(24)",
         OutTemp       => RXDATA_OUT(24),
         Paths         => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => RXDATA(25),
         GlitchData    => RXDATA25_GlitchData,
         OutSignalName => "RXDATA(25)",
         OutTemp       => RXDATA_OUT(25),
         Paths         => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => RXDATA(26),
         GlitchData    => RXDATA26_GlitchData,
         OutSignalName => "RXDATA(26)",
         OutTemp       => RXDATA_OUT(26),
         Paths         => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => RXDATA(27),
         GlitchData    => RXDATA27_GlitchData,
         OutSignalName => "RXDATA(27)",
         OutTemp       => RXDATA_OUT(27),
         Paths         => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => RXDATA(28),
         GlitchData    => RXDATA28_GlitchData,
         OutSignalName => "RXDATA(28)",
         OutTemp       => RXDATA_OUT(28),
         Paths         => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => RXDATA(29),
         GlitchData    => RXDATA29_GlitchData,
         OutSignalName => "RXDATA(29)",
         OutTemp       => RXDATA_OUT(29),
         Paths         => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => RXDATA(30),
         GlitchData    => RXDATA30_GlitchData,
         OutSignalName => "RXDATA(30)",
         OutTemp       => RXDATA_OUT(30),
         Paths         => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => RXDATA(31),
         GlitchData    => RXDATA31_GlitchData,
         OutSignalName => "RXDATA(31)",
         OutTemp       => RXDATA_OUT(31),
         Paths         => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => RXDISPERR(0),
         GlitchData    => RXDISPERR0_GlitchData,
         OutSignalName => "RXDISPERR(0)",
         OutTemp       => RXDISPERR_OUT(0),
         Paths         => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => RXDISPERR(1),
         GlitchData    => RXDISPERR1_GlitchData,
         OutSignalName => "RXDISPERR(1)",
         OutTemp       => RXDISPERR_OUT(1),
         Paths         => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => RXDISPERR(2),
         GlitchData    => RXDISPERR2_GlitchData,
         OutSignalName => "RXDISPERR(2)",
         OutTemp       => RXDISPERR_OUT(2),
         Paths         => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => RXDISPERR(3),
         GlitchData    => RXDISPERR3_GlitchData,
         OutSignalName => "RXDISPERR(3)",
         OutTemp       => RXDISPERR_OUT(3),
         Paths         => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => RXLOSSOFSYNC(0),
         GlitchData    => RXLOSSOFSYNC0_GlitchData,
         OutSignalName => "RXLOSSOFSYNC(0)",
         OutTemp       => RXLOSSOFSYNC_OUT(0),
         Paths         => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => RXLOSSOFSYNC(1),
         GlitchData    => RXLOSSOFSYNC1_GlitchData,
         OutSignalName => "RXLOSSOFSYNC(1)",
         OutTemp       => RXLOSSOFSYNC_OUT(1),
         Paths         => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => RXNOTINTABLE(0),
         GlitchData    => RXNOTINTABLE0_GlitchData,
         OutSignalName => "RXNOTINTABLE(0)",
         OutTemp       => RXNOTINTABLE_OUT(0),
         Paths         => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => RXNOTINTABLE(1),
         GlitchData    => RXNOTINTABLE1_GlitchData,
         OutSignalName => "RXNOTINTABLE(1)",
         OutTemp       => RXNOTINTABLE_OUT(1),
         Paths         => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => RXNOTINTABLE(2),
         GlitchData    => RXNOTINTABLE2_GlitchData,
         OutSignalName => "RXNOTINTABLE(2)",
         OutTemp       => RXNOTINTABLE_OUT(2),
         Paths         => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => RXNOTINTABLE(3),
         GlitchData    => RXNOTINTABLE3_GlitchData,
         OutSignalName => "RXNOTINTABLE(3)",
         OutTemp       => RXNOTINTABLE_OUT(3),
         Paths         => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => RXREALIGN,
         GlitchData    => RXREALIGN_GlitchData,
         OutSignalName => "RXREALIGN",
         OutTemp       => RXREALIGN_OUT,
         Paths         => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => RXRUNDISP(0),
         GlitchData    => RXRUNDISP0_GlitchData,
         OutSignalName => "RXRUNDISP(0)",
         OutTemp       => RXRUNDISP_OUT(0),
         Paths         => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => RXRUNDISP(1),
         GlitchData    => RXRUNDISP1_GlitchData,
         OutSignalName => "RXRUNDISP(1)",
         OutTemp       => RXRUNDISP_OUT(1),
         Paths         => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => RXRUNDISP(2),
         GlitchData    => RXRUNDISP2_GlitchData,
         OutSignalName => "RXRUNDISP(2)",
         OutTemp       => RXRUNDISP_OUT(2),
         Paths         => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => RXRUNDISP(3),
         GlitchData    => RXRUNDISP3_GlitchData,
         OutSignalName => "RXRUNDISP(3)",
         OutTemp       => RXRUNDISP_OUT(3),
         Paths         => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => TXBUFERR,
         GlitchData    => TXBUFERR_GlitchData,
         OutSignalName => "TXBUFERR",
         OutTemp       => TXBUFERR_OUT,
         Paths         => (0 => (TXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => TXKERR(0),
         GlitchData    => TXKERR0_GlitchData,
         OutSignalName => "TXKERR(0)",
         OutTemp       => TXKERR_OUT(0),
         Paths         => (0 => (TXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => TXKERR(1),
         GlitchData    => TXKERR1_GlitchData,
         OutSignalName => "TXKERR(1)",
         OutTemp       => TXKERR_OUT(1),
         Paths         => (0 => (TXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => TXKERR(2),
         GlitchData    => TXKERR2_GlitchData,
         OutSignalName => "TXKERR(2)",
         OutTemp       => TXKERR_OUT(2),
         Paths         => (0 => (TXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => TXKERR(3),
         GlitchData    => TXKERR3_GlitchData,
         OutSignalName => "TXKERR(3)",
         OutTemp       => TXKERR_OUT(3),
         Paths         => (0 => (TXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => TXRUNDISP(0),
         GlitchData    => TXRUNDISP0_GlitchData,
         OutSignalName => "TXRUNDISP(0)",
         OutTemp       => TXRUNDISP_OUT(0),
         Paths         => (0 => (TXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => TXRUNDISP(1),
         GlitchData    => TXRUNDISP1_GlitchData,
         OutSignalName => "TXRUNDISP(1)",
         OutTemp       => TXRUNDISP_OUT(1),
         Paths         => (0 => (TXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => TXRUNDISP(2),
         GlitchData    => TXRUNDISP2_GlitchData,
         OutSignalName => "TXRUNDISP(2)",
         OutTemp       => TXRUNDISP_OUT(2),
         Paths         => (0 => (TXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );
     VitalPathDelay01
       (
         OutSignal     => TXRUNDISP(3),
         GlitchData    => TXRUNDISP3_GlitchData,
         OutSignalName => "TXRUNDISP(3)",
         OutTemp       => TXRUNDISP_OUT(3),
         Paths         => (0 => (TXUSRCLK2_ipd'last_event, out_delay,TRUE)),
         Mode          => VitalTransport,
         Xon           => False,
         MsgOn         => False,
         MsgSeverity   => WARNING
       );

--  Wait signal (input/output pins)
   wait on
     CHBONDDONE_OUT,
     CHBONDO_OUT,
     CONFIGOUT_OUT,
     RXBUFSTATUS_OUT,
     RXCHARISCOMMA_OUT,
     RXCHARISK_OUT,
     RXCHECKINGCRC_OUT,
     RXCLKCORCNT_OUT,
     RXCOMMADET_OUT,
     RXCRCERR_OUT,
     RXDATA_OUT,
     RXDISPERR_OUT,
     RXLOSSOFSYNC_OUT,
     RXNOTINTABLE_OUT,
     RXREALIGN_OUT,
--     RXRECCLK_OUT,
     RXRUNDISP_OUT,
     TXBUFERR_OUT,
     TXKERR_OUT,
--     TXN_OUT,
--     TXP_OUT,
     TXRUNDISP_OUT,
     BREFCLK_ipd,
     BREFCLK2_ipd,
     CHBONDI_ipd,
     CONFIGENABLE_ipd,
     CONFIGIN_ipd,
     ENCHANSYNC_ipd,
     ENMCOMMAALIGN_ipd,
     ENPCOMMAALIGN_ipd,
     LOOPBACK_ipd,
     POWERDOWN_ipd,
     REFCLK_ipd,
     REFCLK2_ipd,
     REFCLKSEL_ipd,
     RXN_ipd,
     RXP_ipd,
     RXPOLARITY_ipd,
     RXRESET_ipd,
     RXUSRCLK_ipd,
     RXUSRCLK2_ipd,
     TXBYPASS8B10B_ipd,
     TXCHARDISPMODE_ipd,
     TXCHARDISPVAL_ipd,
     TXCHARISK_ipd,
     TXDATA_ipd,
     TXFORCECRCERR_ipd,
     TXINHIBIT_ipd,
     TXPOLARITY_ipd,
     TXRESET_ipd,
     TXUSRCLK_ipd,
     TXUSRCLK2_ipd;

   end process TIMING;

     TXN < = TXN_OUT;
     TXP < = TXP_OUT;
     RXRECCLK < = RXRECCLK_OUT;

end GT_V;

----------------------------------------------------
--  
--  Library Name :  unisim
--  Unit    Name :  GT_CUSTOM
--  Unit    Type :  Text Unit
--  
------------------------------------------------------

-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/gt_custom.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 7.1i (H.19)
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Gigabit Transceiver for CUSTOM I/O Standard
-- /___/   /\     Filename : GT_CUSTOM.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:10 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL GT_CUSTOM -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library unisim;
use unisim.VCOMPONENTS.all;

entity GT_CUSTOM is
generic (
		ALIGN_COMMA_MSB : boolean := FALSE;
		CHAN_BOND_LIMIT : integer := 16;
		CHAN_BOND_MODE : string := "OFF";
		CHAN_BOND_OFFSET : integer := 8;
		CHAN_BOND_ONE_SHOT : boolean := FALSE;
		CHAN_BOND_SEQ_1_1 : bit_vector := "00000000000";
		CHAN_BOND_SEQ_1_2 : bit_vector := "00000000000";
		CHAN_BOND_SEQ_1_3 : bit_vector := "00000000000";
		CHAN_BOND_SEQ_1_4 : bit_vector := "00000000000";
		CHAN_BOND_SEQ_2_1 : bit_vector := "00000000000";
		CHAN_BOND_SEQ_2_2 : bit_vector := "00000000000";
		CHAN_BOND_SEQ_2_3 : bit_vector := "00000000000";
		CHAN_BOND_SEQ_2_4 : bit_vector := "00000000000";
		CHAN_BOND_SEQ_2_USE : boolean := FALSE;
		CHAN_BOND_SEQ_LEN : integer := 1;
		CHAN_BOND_WAIT : integer := 8;
		CLK_COR_INSERT_IDLE_FLAG : boolean := FALSE;
		CLK_COR_KEEP_IDLE : boolean := FALSE;
		CLK_COR_REPEAT_WAIT : integer := 1;
		CLK_COR_SEQ_1_1 : bit_vector := "00000000000";
		CLK_COR_SEQ_1_2 : bit_vector := "00000000000";
		CLK_COR_SEQ_1_3 : bit_vector := "00000000000";
		CLK_COR_SEQ_1_4 : bit_vector := "00000000000";
		CLK_COR_SEQ_2_1 : bit_vector := "00000000000";
		CLK_COR_SEQ_2_2 : bit_vector := "00000000000";
		CLK_COR_SEQ_2_3 : bit_vector := "00000000000";
		CLK_COR_SEQ_2_4 : bit_vector := "00000000000";
		CLK_COR_SEQ_2_USE : boolean := FALSE;
		CLK_COR_SEQ_LEN : integer := 1;
		CLK_CORRECT_USE : boolean := TRUE;
		COMMA_10B_MASK : bit_vector := "1111111000";
		CRC_END_OF_PKT : string := "K29_7";
		CRC_FORMAT : string := "USER_MODE";
		CRC_START_OF_PKT : string := "K27_7";
		DEC_MCOMMA_DETECT : boolean := TRUE;
		DEC_PCOMMA_DETECT : boolean := TRUE;
		DEC_VALID_COMMA_ONLY : boolean := TRUE;
		MCOMMA_10B_VALUE : bit_vector := "1100000000";
		MCOMMA_DETECT : boolean := TRUE;
		PCOMMA_10B_VALUE : bit_vector := "0011111000";
		PCOMMA_DETECT : boolean := TRUE;
		REF_CLK_V_SEL : integer := 0;
		RX_BUFFER_USE : boolean := TRUE;
		RX_CRC_USE : boolean := FALSE;
		RX_DATA_WIDTH : integer := 2;
		RX_DECODE_USE : boolean := TRUE;
		RX_LOS_INVALID_INCR : integer := 1;
		RX_LOS_THRESHOLD : integer := 4;
		RX_LOSS_OF_SYNC_FSM : boolean := TRUE;
		SERDES_10B : boolean := FALSE;
		TERMINATION_IMP : integer := 50;
		TX_BUFFER_USE : boolean := TRUE;
		TX_CRC_FORCE_VALUE : bit_vector := "11010110";
		TX_CRC_USE : boolean := FALSE;
		TX_DATA_WIDTH : integer := 2;
		TX_DIFF_CTRL : integer := 500;
		TX_PREEMPHASIS : integer := 0


  );

port (
		CHBONDDONE : out std_ulogic;
		CHBONDO : out std_logic_vector(3 downto 0);
		CONFIGOUT : out std_ulogic;
		RXBUFSTATUS : out std_logic_vector(1 downto 0);
		RXCHARISCOMMA : out std_logic_vector(3 downto 0);
		RXCHARISK : out std_logic_vector(3 downto 0);
		RXCHECKINGCRC : out std_ulogic;
		RXCLKCORCNT : out std_logic_vector(2 downto 0);
		RXCOMMADET : out std_ulogic;
		RXCRCERR : out std_ulogic;
		RXDATA : out std_logic_vector(31 downto 0);
		RXDISPERR : out std_logic_vector(3 downto 0);
		RXLOSSOFSYNC : out std_logic_vector(1 downto 0);
		RXNOTINTABLE : out std_logic_vector(3 downto 0);
		RXREALIGN : out std_ulogic;
		RXRECCLK : out std_ulogic;
		RXRUNDISP : out std_logic_vector(3 downto 0);
		TXBUFERR : out std_ulogic;
		TXKERR : out std_logic_vector(3 downto 0);
		TXN : out std_ulogic;
		TXP : out std_ulogic;
		TXRUNDISP : out std_logic_vector(3 downto 0);

		BREFCLK : in std_ulogic := 'X';
		BREFCLK2 : in std_ulogic := 'X';
		CHBONDI : in std_logic_vector(3 downto 0);
		CONFIGENABLE : in std_ulogic;
		CONFIGIN : in std_ulogic;
		ENCHANSYNC : in std_ulogic;
		ENMCOMMAALIGN : in std_ulogic;
		ENPCOMMAALIGN : in std_ulogic;
		LOOPBACK : in std_logic_vector(1 downto 0);
		POWERDOWN : in std_ulogic;
		REFCLK : in std_ulogic;
		REFCLK2 : in std_ulogic;
		REFCLKSEL : in std_ulogic;
		RXN : in std_ulogic;
		RXP : in std_ulogic;
		RXPOLARITY : in std_ulogic;
		RXRESET : in std_ulogic;
		RXUSRCLK : in std_ulogic;
		RXUSRCLK2 : in std_ulogic;
		TXBYPASS8B10B : in std_logic_vector(3 downto 0);
		TXCHARDISPMODE : in std_logic_vector(3 downto 0);
		TXCHARDISPVAL : in std_logic_vector(3 downto 0);
		TXCHARISK : in std_logic_vector(3 downto 0);
		TXDATA : in std_logic_vector(31 downto 0);
		TXFORCECRCERR : in std_ulogic;
		TXINHIBIT : in std_ulogic;
		TXPOLARITY : in std_ulogic;
		TXRESET : in std_ulogic;
		TXUSRCLK : in std_ulogic;
		TXUSRCLK2 : in std_ulogic
     );
end GT_CUSTOM;



-- Architecture body --

architecture GT_CUSTOM_V of GT_CUSTOM is


begin
-- GT Instatiation (port map, generic map)
GT_inst : GT
	generic map (
		ALIGN_COMMA_MSB => ALIGN_COMMA_MSB,
		CHAN_BOND_LIMIT => CHAN_BOND_LIMIT,
		CHAN_BOND_MODE => CHAN_BOND_MODE,
		CHAN_BOND_OFFSET => CHAN_BOND_OFFSET,
		CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT,
		CHAN_BOND_SEQ_1_1 => CHAN_BOND_SEQ_1_1,
		CHAN_BOND_SEQ_1_2 => CHAN_BOND_SEQ_1_2,
		CHAN_BOND_SEQ_1_3 => CHAN_BOND_SEQ_1_3,
		CHAN_BOND_SEQ_1_4 => CHAN_BOND_SEQ_1_4,
		CHAN_BOND_SEQ_2_1 => CHAN_BOND_SEQ_2_1,
		CHAN_BOND_SEQ_2_2 => CHAN_BOND_SEQ_2_2,
		CHAN_BOND_SEQ_2_3 => CHAN_BOND_SEQ_2_3,
		CHAN_BOND_SEQ_2_4 => CHAN_BOND_SEQ_2_4,
		CHAN_BOND_SEQ_2_USE => CHAN_BOND_SEQ_2_USE,
		CHAN_BOND_SEQ_LEN => CHAN_BOND_SEQ_LEN,
		CHAN_BOND_WAIT => CHAN_BOND_WAIT,
		CLK_COR_INSERT_IDLE_FLAG => CLK_COR_INSERT_IDLE_FLAG,
		CLK_COR_KEEP_IDLE => CLK_COR_KEEP_IDLE,
		CLK_COR_REPEAT_WAIT => CLK_COR_REPEAT_WAIT,
		CLK_COR_SEQ_1_1 => CLK_COR_SEQ_1_1,
		CLK_COR_SEQ_1_2 => CLK_COR_SEQ_1_2,
		CLK_COR_SEQ_1_3 => CLK_COR_SEQ_1_3,
		CLK_COR_SEQ_1_4 => CLK_COR_SEQ_1_4,
		CLK_COR_SEQ_2_1 => CLK_COR_SEQ_2_1,
		CLK_COR_SEQ_2_2 => CLK_COR_SEQ_2_2,
		CLK_COR_SEQ_2_3 => CLK_COR_SEQ_2_3,
		CLK_COR_SEQ_2_4 => CLK_COR_SEQ_2_4,
		CLK_COR_SEQ_2_USE => CLK_COR_SEQ_2_USE,
		CLK_COR_SEQ_LEN => CLK_COR_SEQ_LEN,
		CLK_CORRECT_USE => CLK_CORRECT_USE,
		COMMA_10B_MASK => COMMA_10B_MASK,
		CRC_END_OF_PKT => CRC_END_OF_PKT,
		CRC_FORMAT => CRC_FORMAT,
		CRC_START_OF_PKT => CRC_START_OF_PKT,
		DEC_MCOMMA_DETECT => DEC_MCOMMA_DETECT,
		DEC_PCOMMA_DETECT => DEC_PCOMMA_DETECT,
		DEC_VALID_COMMA_ONLY => DEC_VALID_COMMA_ONLY,
		MCOMMA_10B_VALUE => MCOMMA_10B_VALUE,
		MCOMMA_DETECT => MCOMMA_DETECT,
		PCOMMA_10B_VALUE => PCOMMA_10B_VALUE,
		PCOMMA_DETECT => PCOMMA_DETECT,
		REF_CLK_V_SEL => REF_CLK_V_SEL,
		RX_BUFFER_USE => RX_BUFFER_USE,
		RX_CRC_USE => RX_CRC_USE,
		RX_DATA_WIDTH => RX_DATA_WIDTH,
		RX_DECODE_USE => RX_DECODE_USE,
		RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR,
		RX_LOS_THRESHOLD => RX_LOS_THRESHOLD,
		RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM,
		SERDES_10B => SERDES_10B,
		TERMINATION_IMP => TERMINATION_IMP,
		TX_BUFFER_USE => TX_BUFFER_USE,
		TX_CRC_FORCE_VALUE => TX_CRC_FORCE_VALUE,
		TX_CRC_USE => TX_CRC_USE,
		TX_DATA_WIDTH => TX_DATA_WIDTH,
		TX_DIFF_CTRL => TX_DIFF_CTRL,
		TX_PREEMPHASIS => TX_PREEMPHASIS
)
port map (
		CHBONDDONE => CHBONDDONE,
		CHBONDO => CHBONDO,
		CONFIGOUT => CONFIGOUT,
		RXBUFSTATUS => RXBUFSTATUS,
		RXCHARISCOMMA => RXCHARISCOMMA,
		RXCHARISK => RXCHARISK,
		RXCHECKINGCRC => RXCHECKINGCRC,
		RXCLKCORCNT => RXCLKCORCNT,
		RXCOMMADET => RXCOMMADET,
		RXCRCERR => RXCRCERR,
		RXDATA => RXDATA,
		RXDISPERR => RXDISPERR,
		RXLOSSOFSYNC => RXLOSSOFSYNC,
		RXNOTINTABLE => RXNOTINTABLE,
		RXREALIGN => RXREALIGN,
		RXRECCLK => RXRECCLK,
		RXRUNDISP => RXRUNDISP,
		TXBUFERR => TXBUFERR,
		TXKERR => TXKERR,
		TXN => TXN,
		TXP => TXP,
		TXRUNDISP => TXRUNDISP,
		BREFCLK => BREFCLK,
		BREFCLK2 => BREFCLK2,
		CHBONDI => CHBONDI,
		CONFIGENABLE => CONFIGENABLE,
		CONFIGIN => CONFIGIN,
		ENCHANSYNC => ENCHANSYNC,
		ENMCOMMAALIGN => ENMCOMMAALIGN,
		ENPCOMMAALIGN => ENPCOMMAALIGN,
		LOOPBACK => LOOPBACK,
		POWERDOWN => POWERDOWN,
		REFCLK => REFCLK,
		REFCLK2 => REFCLK2,
		REFCLKSEL => REFCLKSEL,
		RXN => RXN,
		RXP => RXP,
		RXPOLARITY => RXPOLARITY,
		RXRESET => RXRESET,
		RXUSRCLK => RXUSRCLK,
		RXUSRCLK2 => RXUSRCLK2,
		TXBYPASS8B10B => TXBYPASS8B10B,
		TXCHARDISPMODE => TXCHARDISPMODE,
		TXCHARDISPVAL => TXCHARDISPVAL,
		TXCHARISK => TXCHARISK,
		TXDATA => TXDATA,
		TXFORCECRCERR => TXFORCECRCERR,
		TXINHIBIT => TXINHIBIT,
		TXPOLARITY => TXPOLARITY,
		TXRESET => TXRESET,
		TXUSRCLK => TXUSRCLK,
		TXUSRCLK2 => TXUSRCLK2

);

end GT_CUSTOM_V;

----------------------------------------------------
--  
--  Library Name :  GTS
--  Unit    Name :  MGT_custom
--  Unit    Type :  Text Unit
--  
------------------------------------------------------
-- Module MGT_custom
-- Generated by Xilinx Architecture Wizard
-- VHDL
-- Written for synthesis tool: Synplicity
-- Xilinx Device: XC2VP7-FF672-6

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.all;
-- synopsys translate_on

entity MGT_custom is
    port (
        CONFIGENABLE : in std_logic;
        CONFIGIN : in std_logic;
        ENMCOMMAALIGN : in std_logic;
        ENPCOMMAALIGN : in std_logic;
        ENCHANSYNC : in std_logic;
        LOOPBACK : in std_logic_vector (1 downto 0);
        POWERDOWN : in std_logic;
        REFCLK : in std_logic;
        REFCLK2 : in std_logic;
        REFCLKSEL : in std_logic;
        BREFCLK : in std_logic;
        BREFCLK2 : in std_logic;
        RXN : in std_logic;
        RXP : in std_logic;
        RXPOLARITY : in std_logic;
        RXRESET : in std_logic;
        RXUSRCLK : in std_logic;
        RXUSRCLK2 : in std_logic;
        TXBYPASS8B10B : in std_logic_vector (1 downto 0);
        TXCHARDISPMODE : in std_logic_vector (1 downto 0);
        TXCHARDISPVAL : in std_logic_vector (1 downto 0);
        TXCHARISK : in std_logic_vector (1 downto 0);
        TXDATA : in std_logic_vector (15 downto 0);
        TXFORCECRCERR : in std_logic;
        TXINHIBIT : in std_logic;
        TXPOLARITY : in std_logic;
        TXRESET : in std_logic;
        TXUSRCLK : in std_logic;
        TXUSRCLK2 : in std_logic;
        CHBONDDONE : out std_logic;
        CONFIGOUT : out std_logic;
        RXBUFSTATUS : out std_logic_vector (1 downto 0);
        RXCHARISCOMMA : out std_logic_vector (1 downto 0);
        RXCHARISK : out std_logic_vector (1 downto 0);
        RXCHECKINGCRC : out std_logic;
        RXCLKCORCNT : out std_logic_vector (2 downto 0);
        RXCOMMADET : out std_logic;
        RXCRCERR : out std_logic;
        RXDATA : out std_logic_vector (15 downto 0);
        RXDISPERR : out std_logic_vector (1 downto 0);
        RXLOSSOFSYNC : out std_logic_vector (1 downto 0);
        RXNOTINTABLE : out std_logic_vector (1 downto 0);
        RXREALIGN : out std_logic;
        RXRECCLK : out std_logic;
        RXRUNDISP : out std_logic_vector (1 downto 0);
        TXBUFERR : out std_logic;
        TXKERR : out std_logic_vector (1 downto 0);
        TXN : out std_logic;
        TXP : out std_logic;
        TXRUNDISP : out std_logic_vector (1 downto 0));
end MGT_custom;



architecture STRUCT of MGT_custom is
   signal GND : std_logic_vector (3 downto 0);
   signal GND1 : std_logic_vector (31 downto 0);
   signal RXCHARISCOMMA_float : std_logic_vector (1 downto 0);
   signal RXCHARISK_float : std_logic_vector (1 downto 0);
   signal RXDATA_float : std_logic_vector (15 downto 0);
   signal RXDISPERR_float : std_logic_vector (1 downto 0);
   signal RXNOTINTABLE_float : std_logic_vector (1 downto 0);
   signal RXRUNDISP_float : std_logic_vector (1 downto 0);
   signal TXKERR_float : std_logic_vector (1 downto 0);
   signal TXRUNDISP_float : std_logic_vector (1 downto 0);


   component GT_CUSTOM
    generic( 
       ALIGN_COMMA_MSB : boolean := FALSE;
       CHAN_BOND_LIMIT : integer := 16;
       CHAN_BOND_MODE : string := "OFF";
       CHAN_BOND_OFFSET : integer := 8;
       CHAN_BOND_ONE_SHOT : boolean := FALSE;
       CHAN_BOND_SEQ_1_1 : bit_vector := "00000000000";
       CHAN_BOND_SEQ_1_2 : bit_vector := "00000000000";
       CHAN_BOND_SEQ_1_3 : bit_vector := "00000000000";
       CHAN_BOND_SEQ_1_4 : bit_vector := "00000000000";
       CHAN_BOND_SEQ_2_1 : bit_vector := "00000000000";
       CHAN_BOND_SEQ_2_2 : bit_vector := "00000000000";
       CHAN_BOND_SEQ_2_3 : bit_vector := "00000000000";
       CHAN_BOND_SEQ_2_4 : bit_vector := "00000000000";
       CHAN_BOND_SEQ_2_USE : boolean := FALSE;
       CHAN_BOND_SEQ_LEN : integer := 1;
       CHAN_BOND_WAIT : integer := 8;
       CLK_COR_INSERT_IDLE_FLAG : boolean := FALSE;
       CLK_COR_KEEP_IDLE : boolean := FALSE;
       CLK_COR_REPEAT_WAIT : integer := 1;
       CLK_COR_SEQ_1_1 : bit_vector := "00000000000";
       CLK_COR_SEQ_1_2 : bit_vector := "00000000000";
       CLK_COR_SEQ_1_3 : bit_vector := "00000000000";
       CLK_COR_SEQ_1_4 : bit_vector := "00000000000";
       CLK_COR_SEQ_2_1 : bit_vector := "00000000000";
       CLK_COR_SEQ_2_2 : bit_vector := "00000000000";
       CLK_COR_SEQ_2_3 : bit_vector := "00000000000";
       CLK_COR_SEQ_2_4 : bit_vector := "00000000000";
       CLK_COR_SEQ_2_USE : boolean := FALSE;
       CLK_COR_SEQ_LEN : integer := 1;
       CLK_CORRECT_USE : boolean := TRUE;
       COMMA_10B_MASK : bit_vector := "1111111000";
       CRC_END_OF_PKT : string := "K29_7";
       CRC_FORMAT : string := "USER_MODE";
       CRC_START_OF_PKT : string := "K27_7";
       DEC_MCOMMA_DETECT : boolean := TRUE;
       DEC_PCOMMA_DETECT : boolean := TRUE;
       DEC_VALID_COMMA_ONLY : boolean := TRUE;
       MCOMMA_10B_VALUE : bit_vector := "1100000000";
       MCOMMA_DETECT : boolean := TRUE;
       PCOMMA_10B_VALUE : bit_vector := "0011111000";
       PCOMMA_DETECT : boolean := TRUE;
       REF_CLK_V_SEL : integer := 1;		--- < < < < ----
       RX_BUFFER_USE : boolean := TRUE;
       RX_CRC_USE : boolean := FALSE;
       RX_DATA_WIDTH : integer := 2;
       RX_DECODE_USE : boolean := TRUE;
       RX_LOS_INVALID_INCR : integer := 1;
       RX_LOS_THRESHOLD : integer := 4;
       RX_LOSS_OF_SYNC_FSM : boolean := TRUE;
       SERDES_10B : boolean := FALSE;
       TERMINATION_IMP : integer := 50;
       TX_BUFFER_USE : boolean := TRUE;
       TX_CRC_FORCE_VALUE : bit_vector := "11010110";
       TX_CRC_USE : boolean := FALSE;
       TX_DATA_WIDTH : integer := 2;
       TX_DIFF_CTRL : integer := 500;
       TX_PREEMPHASIS : integer := 0
     );
     port (
       CHBONDI : in std_logic_vector (3 downto 0);
       CONFIGENABLE : in std_logic;
       CONFIGIN : in std_logic;
       ENMCOMMAALIGN : in std_logic;
       ENPCOMMAALIGN : in std_logic;
       ENCHANSYNC : in std_logic;
       LOOPBACK : in std_logic_vector (1 downto 0);
       POWERDOWN : in std_logic;
       REFCLK : in std_logic;
       REFCLK2 : in std_logic;
       REFCLKSEL : in std_logic;
       BREFCLK : in std_logic;
       BREFCLK2 : in std_logic;
       RXN : in std_logic;
       RXP : in std_logic;
       RXPOLARITY : in std_logic;
       RXRESET : in std_logic;
       RXUSRCLK : in std_logic;
       RXUSRCLK2 : in std_logic;
       TXBYPASS8B10B : in std_logic_vector (3 downto 0);
       TXCHARDISPMODE : in std_logic_vector (3 downto 0);
       TXCHARDISPVAL : in std_logic_vector (3 downto 0);
       TXCHARISK : in std_logic_vector (3 downto 0);
       TXDATA : in std_logic_vector (31 downto 0);
       TXFORCECRCERR : in std_logic;
       TXINHIBIT : in std_logic;
       TXPOLARITY : in std_logic;
       TXRESET : in std_logic;
       TXUSRCLK : in std_logic;
       TXUSRCLK2 : in std_logic;
       CHBONDDONE : out std_logic;
       CHBONDO : out std_logic_vector (3 downto 0);
       CONFIGOUT : out std_logic;
       RXBUFSTATUS : out std_logic_vector (1 downto 0);
       RXCHARISCOMMA : out std_logic_vector (3 downto 0);
       RXCHARISK : out std_logic_vector (3 downto 0);
       RXCHECKINGCRC : out std_logic;
       RXCLKCORCNT : out std_logic_vector (2 downto 0);
       RXCOMMADET : out std_logic;
       RXCRCERR : out std_logic;
       RXDATA : out std_logic_vector (31 downto 0);
       RXDISPERR : out std_logic_vector (3 downto 0);
       RXLOSSOFSYNC : out std_logic_vector (1 downto 0);
       RXNOTINTABLE : out std_logic_vector (3 downto 0);
       RXREALIGN : out std_logic;
       RXRECCLK : out std_logic;
       RXRUNDISP : out std_logic_vector (3 downto 0);
       TXBUFERR : out std_logic;
       TXKERR : out std_logic_vector (3 downto 0);
       TXN : out std_logic;
       TXP : out std_logic;
       TXRUNDISP : out std_logic_vector (3 downto 0)
       );
   end component;

begin
   GT_CUSTOM_INST : GT_CUSTOM
    Generic map (
      ALIGN_COMMA_MSB => TRUE,
      CHAN_BOND_LIMIT => 16,
      CHAN_BOND_MODE => "OFF",
      CHAN_BOND_OFFSET => 8,
      CHAN_BOND_ONE_SHOT => FALSE,
      CHAN_BOND_SEQ_1_1 => "00000000000",
      CHAN_BOND_SEQ_1_2 => "00000000000",
      CHAN_BOND_SEQ_1_3 => "00000000000",
      CHAN_BOND_SEQ_1_4 => "00000000000",
      CHAN_BOND_SEQ_2_1 => "00000000000",
      CHAN_BOND_SEQ_2_2 => "00000000000",
      CHAN_BOND_SEQ_2_3 => "00000000000",
      CHAN_BOND_SEQ_2_4 => "00000000000",
      CHAN_BOND_SEQ_2_USE => FALSE,
      CHAN_BOND_SEQ_LEN => 1,
      CHAN_BOND_WAIT => 8,
      CLK_CORRECT_USE => FALSE,
      CLK_COR_INSERT_IDLE_FLAG => FALSE,
      CLK_COR_KEEP_IDLE => FALSE,
      CLK_COR_REPEAT_WAIT => 1,
      CLK_COR_SEQ_1_1 => "00000000000",
      CLK_COR_SEQ_1_2 => "00000000000",
      CLK_COR_SEQ_1_3 => "00000000000",
      CLK_COR_SEQ_1_4 => "00000000000",
      CLK_COR_SEQ_2_1 => "00000000000",
      CLK_COR_SEQ_2_2 => "00000000000",
      CLK_COR_SEQ_2_3 => "00000000000",
      CLK_COR_SEQ_2_4 => "00000000000",
      CLK_COR_SEQ_2_USE => FALSE,
      CLK_COR_SEQ_LEN => 1,
      COMMA_10B_MASK => "1111111000",
      CRC_END_OF_PKT => "K29_7",
      CRC_FORMAT => "USER_MODE",
      CRC_START_OF_PKT => "K27_7",
      DEC_MCOMMA_DETECT => TRUE,
      DEC_PCOMMA_DETECT => TRUE,
      DEC_VALID_COMMA_ONLY => TRUE,
      MCOMMA_10B_VALUE => "1100000000",
      MCOMMA_DETECT => TRUE,
      PCOMMA_10B_VALUE => "0011111000",
      PCOMMA_DETECT => TRUE,
      RX_BUFFER_USE => TRUE,
      RX_CRC_USE => FALSE,
      RX_DATA_WIDTH => 2,
      RX_DECODE_USE => TRUE,
      RX_LOSS_OF_SYNC_FSM => TRUE,
      RX_LOS_INVALID_INCR => 1,
      RX_LOS_THRESHOLD => 4,
      TERMINATION_IMP => 50,
      SERDES_10B => FALSE,
      TX_BUFFER_USE => TRUE,
      TX_CRC_FORCE_VALUE => "11010110",
      TX_CRC_USE => FALSE,
      TX_DATA_WIDTH => 2,
      TX_DIFF_CTRL => 500,
      TX_PREEMPHASIS => 0,
      REF_CLK_V_SEL => 0)
     port map (
      CHBONDI(3 downto 0) => GND(3 downto 0),
      CONFIGENABLE => CONFIGENABLE,
      CONFIGIN => CONFIGIN,
      ENMCOMMAALIGN => ENMCOMMAALIGN,
      ENPCOMMAALIGN => ENPCOMMAALIGN,
      ENCHANSYNC => ENCHANSYNC,
      LOOPBACK(1 downto 0) => LOOPBACK(1 downto 0),
      POWERDOWN => POWERDOWN,
      REFCLK => REFCLK,
      REFCLK2 => REFCLK2,
      REFCLKSEL => REFCLKSEL,
      BREFCLK => BREFCLK,
      BREFCLK2 => BREFCLK2,
      RXN => RXN,
      RXP => RXP,
      RXPOLARITY => RXPOLARITY,
      RXRESET => RXRESET,
      RXUSRCLK => RXUSRCLK,
      RXUSRCLK2 => RXUSRCLK2,
      TXBYPASS8B10B(1 downto 0) => TXBYPASS8B10B(1 downto 0),
      TXBYPASS8B10B(3 downto 2) => GND(1 downto 0),
      TXCHARDISPMODE(1 downto 0) => TXCHARDISPMODE(1 downto 0),
      TXCHARDISPMODE(3 downto 2) => GND(1 downto 0),
      TXCHARDISPVAL(1 downto 0) => TXCHARDISPVAL(1 downto 0),
      TXCHARDISPVAL(3 downto 2) => GND(1 downto 0),
      TXCHARISK(1 downto 0) => TXCHARISK(1 downto 0),
      TXCHARISK(3 downto 2) => GND(1 downto 0),
      TXDATA(15 downto 0) => TXDATA(15 downto 0),
      TXDATA(31 downto 16) => GND1(15 downto 0),
      TXFORCECRCERR => TXFORCECRCERR,
      TXINHIBIT => TXINHIBIT,
      TXPOLARITY => TXPOLARITY,
      TXRESET => TXRESET,
      TXUSRCLK => TXUSRCLK,
      TXUSRCLK2 => TXUSRCLK2,
      CHBONDDONE => CHBONDDONE,
      CONFIGOUT => CONFIGOUT,
      RXBUFSTATUS(1 downto 0) => RXBUFSTATUS(1 downto 0),
      RXCHARISCOMMA(1 downto 0) => RXCHARISCOMMA(1 downto 0),
      RXCHARISCOMMA(3 downto 2) => RXCHARISCOMMA_float(1 downto 0),
      RXCHARISK(1 downto 0) => RXCHARISK(1 downto 0),
      RXCHARISK(3 downto 2) => RXCHARISK_float(1 downto 0),
      RXCHECKINGCRC => RXCHECKINGCRC,
      RXCLKCORCNT(2 downto 0) => RXCLKCORCNT(2 downto 0),
      RXCOMMADET => RXCOMMADET,
      RXCRCERR => RXCRCERR,
      RXDATA(15 downto 0) => RXDATA(15 downto 0),
      RXDATA(31 downto 16) => RXDATA_float(15 downto 0),
      RXDISPERR(1 downto 0) => RXDISPERR(1 downto 0),
      RXDISPERR(3 downto 2) => RXDISPERR_float(1 downto 0),
      RXLOSSOFSYNC(1 downto 0) => RXLOSSOFSYNC(1 downto 0),
      RXNOTINTABLE(1 downto 0) => RXNOTINTABLE(1 downto 0),
      RXNOTINTABLE(3 downto 2) => RXNOTINTABLE_float(1 downto 0),
      RXREALIGN => RXREALIGN,
      RXRECCLK => RXRECCLK,
      RXRUNDISP(1 downto 0) => RXRUNDISP(1 downto 0),
      RXRUNDISP(3 downto 2) => RXRUNDISP_float(1 downto 0),
      TXBUFERR => TXBUFERR,
      TXKERR(1 downto 0) => TXKERR(1 downto 0),
      TXKERR(3 downto 2) => TXKERR_float(1 downto 0),
      TXN => TXN,
      TXP => TXP,
      TXRUNDISP(1 downto 0) => TXRUNDISP(1 downto 0),
      TXRUNDISP(3 downto 2) => TXRUNDISP_float(1 downto 0));

   GND < = "0000";
   GND1 < = "00000000000000000000000000000000";
end STRUCT;



----------------------------------------------------
--  
--  Library Name :  GTS
--  Unit    Name :  Hamming4
--  Unit    Type :  Text Unit
--  
------------------------------------------------------


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
-- use work.EDAC.all;

entity Hamming4 is
   port(
      DataOut:       in    std_logic_vector(0 to 3);    -- Output data bits
      CheckOut:      out   std_logic_vector(0 to 3);    -- Output check bits

      DataIn:        in    std_logic_vector(0 to 3);    -- Input data bits
      CheckIn:       in    std_logic_vector(0 to 3);    -- Input check bits

      DataCorr:      out   std_logic_vector(0 to 3);    -- Corrected data bits
      SingleErr:     out   Std_ULogic;          -- Single error
      DoubleErr:     out   Std_ULogic;          -- Double error
      MultipleErr:   out   Std_ULogic          -- Uncorrectable error
   );
end Hamming4;



architecture RTL of Hamming4 is

 begin

   process (DataOut,DataIn,CheckIn)
      variable PgenL:         Std_Logic_Vector(0 to 3);  -- Generated parity
      variable SyndL:         Std_Logic_Vector(0 to 3);  -- Syndrome
      variable FlipL:         Std_Logic_Vector(0 to 3);  -- Bits to invert
      variable ChipL:         Std_Logic_Vector(0 to 3);  -- Errors in parity

     begin

      -- Check bit generator
      PgenL(0) := not (DataIn(0) xor DataIn(1) xor DataIn(2));
      PgenL(1) :=      DataIn(0) xor DataIn(1) xor DataIn(3);
      PgenL(2) := not (DataIn(0) xor DataIn(2) xor DataIn(3));
      PgenL(3) :=      DataIn(1) xor DataIn(2) xor DataIn(3);

      -- Syndrome bit generator
      SyndL(0) := PgenL(0) xor not CheckIn(0);
      SyndL(1) := PgenL(1) xor not CheckIn(1);
      SyndL(2) := PgenL(2) xor     CheckIn(2);
      SyndL(3) := PgenL(3) xor     CheckIn(3);

      -- Bit corrector
      if SyndL="1110" then
         FlipL(0) := '1';
      else
         FlipL(0) := '0';
      end if;
      if SyndL="1101" then
         FlipL(1) := '1';
      else
         FlipL(1) := '0';
      end if;
      if SyndL="1011" then
         FlipL(2) := '1';
      else
         FlipL(2) := '0';
      end if;
      if SyndL="0111" then
         FlipL(3) := '1';
      else
         FlipL(3) := '0';
      end if;

      -- Single error in check bits
      if SyndL="0001" then
         ChipL(0) := '1';
      else
         ChipL(0) := '0';
      end if;
      if SyndL="0010" then
         ChipL(1) := '1';
      else
         ChipL(1) := '0';
      end if;
      if SyndL="0100" then
         ChipL(2) := '1';
      else
         ChipL(2) := '0';
      end if;
      if SyndL="1000" then
         ChipL(3) := '1';
      else
         ChipL(3) := '0';
      end if;

      -- Corrected data
      DataCorr(0) < = DataIn(0) xor FlipL(0);
      DataCorr(1) < = DataIn(1) xor FlipL(1);
      DataCorr(2) < = DataIn(2) xor FlipL(2);
      DataCorr(3) < = DataIn(3) xor FlipL(3);

      -- Check bits
      CheckOut(0) < = not (not (DataOut(0) xor DataOut(1) xor DataOut(2)));
      CheckOut(1) < = not (     DataOut(0) xor DataOut(1) xor DataOut(3));
      CheckOut(2) < =     (not (DataOut(0) xor DataOut(2) xor DataOut(3)));
      CheckOut(3) < =     (     DataOut(1) xor DataOut(2) xor DataOut(3));

      -- Single correctable error flag
      SingleErr   < = (FlipL(0) or FlipL(1) or FlipL(2) or FlipL(3)) xor
                     (ChipL(0) or ChipL(1) or ChipL(2) or ChipL(3));

      -- double correctable error flag
      DoubleErr   < = '0';

      -- Uncorrectable error flag
      if SyndL="0011" or SyndL="0101" or
         SyndL="0110" or SyndL="1001" or
         SyndL="1010" or SyndL="1100" or
         SyndL="1111" then
         MultipleErr    < = '1';
      else
         MultipleErr    < = '0';
      end if;
   end process;
 end RTL;



----------------------------------------------------
--  
--  Library Name :  GTS
--  Unit    Name :  cmd_dec_ctrl
--  Unit    Type :  State Machine
--  
------------------------------------------------------
 
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.STD_LOGIC_SIGNED.all;
use ieee.NUMERIC_STD.all;
library GTS;
use GTS.gts_pack.all;
library synplify;
use synplify.attributes.all;
 
 
entity cmd_dec_ctrl is
  port (
        L1A : out std_logic_vector(15 downto 0 );
        reset : out std_logic;
        event_num : out std_logic_vector(23 downto 0 );
        bcast_strobe : out std_logic;
        bcast_out : out std_logic_vector(7 downto 0 );
        L1A_arrived : out std_logic;
        bclk : in std_logic;
        lreset : in std_logic;
        nib : in std_logic_vector(0 to 3 );
        outofsync : in std_logic
        );
 
end cmd_dec_ctrl;
 
 
architecture cmd_dec_ctrl of cmd_dec_ctrl is
 
  signal index : unsigned(3 downto 0 );
  signal nib_count : unsigned(3 downto 0 );
  signal payload : std_logic_vector(63 downto 0 );
 
  type visual_S0_states is (S0, S1, S10, S2, S9, S3, S4, S5, S6, S8);
  signal visual_S0_current : visual_S0_states;
 
 
begin
 
 
 
  -- Synchronous process
  cmd_dec_ctrl_S0:
  process (bclk, lreset)
  begin
 
    if (lreset = '1') then
      index < ="0000";
      L1A_arrived< ='0';
      reset< ='0';
      visual_S0_current < = S0;
    elsif (bclk'event and bclk = '1') then
 
      case visual_S0_current is
        when S0 =>
          if (nib = "1111" and outofsync = '0') then  --  start of frame
            visual_S0_current < = S9;
          else
            visual_S0_current < = S0;
          end if;
 
        when S1 =>
          case index is
            when "0000" => payload(3 downto 0) < = nib;
            when "0001" => payload(7 downto 4) < =nib;
            when "0010" => payload(11 downto 8)< =nib;
            when "0011" => payload(15 downto 12) < = nib;
            when "0100" => payload(19 downto 16) < =nib;
            when "0101" => payload(23 downto 20)< =nib;
            when "0110" => payload(27 downto 24) < = nib;
            when "0111" => payload(31 downto 28) < =nib;
            when "1000" => payload(35 downto 32)< =nib;
            when "1001" => payload(39 downto 36) < = nib;
            when "1010" => payload(43 downto 40) < =nib;
            when "1011" => payload(47 downto 44)< =nib;
            when "1100" => payload(51 downto 48) < = nib;
            when "1101" => payload(55 downto 52) < =nib;
            when "1110" => payload(59 downto 56)< =nib;
            when "1111" => payload(63 downto 60)< =nib;
            when others => payload< =(others =>'0');
          end case;
          visual_S0_current < = S2;
 
        when S10 =>
          if (index = nib_count) then
            visual_S0_current < = S3;
          else
            case index is
              when "0000" => payload(3 downto 0) < = nib;
              when "0001" => payload(7 downto 4) < =nib;
              when "0010" => payload(11 downto 8)< =nib;
              when "0011" => payload(15 downto 12) < = nib;
              when "0100" => payload(19 downto 16) < =nib;
              when "0101" => payload(23 downto 20)< =nib;
              when "0110" => payload(27 downto 24) < = nib;
              when "0111" => payload(31 downto 28) < =nib;
              when "1000" => payload(35 downto 32)< =nib;
              when "1001" => payload(39 downto 36) < = nib;
              when "1010" => payload(43 downto 40) < =nib;
              when "1011" => payload(47 downto 44)< =nib;
              when "1100" => payload(51 downto 48) < = nib;
              when "1101" => payload(55 downto 52) < =nib;
              when "1110" => payload(59 downto 56)< =nib;
              when "1111" => payload(63 downto 60)< =nib;
              when others => payload< =(others =>'0');
            end case;
            visual_S0_current < = S2;
          end if;
 
        when S2 =>
          index< =index+1;
          visual_S0_current < = S10;
 
        when S9 =>
          nib_count < = unsigned (nib);
          visual_S0_current < = S1;
 
        when S3 =>
          if (payload(3 downto 0) = "0000") then
            L1A< = payload(19 downto 4);
            event_num< = payload(43 downto 20);
            L1A_arrived< ='1';
            visual_S0_current < = S4;
          elsif (payload(3 downto 0) = "0001") then
            reset< ='1';
            visual_S0_current < = S6;
          else
            index < ="0000";
            L1A_arrived< ='0';
            reset< ='0';
            visual_S0_current < = S0;
          end if;
 
        when S4 =>
          visual_S0_current < = S5;
 
        when S5 =>
          index < ="0000";
          L1A_arrived< ='0';
          reset< ='0';
          visual_S0_current < = S0;
 
        when S6 =>
          visual_S0_current < = S8;
 
        when S8 =>
          index < ="0000";
          L1A_arrived< ='0';
          reset< ='0';
          visual_S0_current < = S0;
 
        when others =>
 
          index < ="0000";
          L1A_arrived< ='0';
          reset< ='0';
          visual_S0_current < = S0;
      end case;
    end if;
  end process cmd_dec_ctrl_S0;
 
end cmd_dec_ctrl;
----------------------------------------------------
--  
--  Library Name :  GTS
--  Unit    Name :  cmd_dec
--  Unit    Type :  Block Diagram
--  
------------------------------------------------------
 
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.STD_LOGIC_SIGNED.all;
use ieee.NUMERIC_STD.all;
library GTS;
use GTS.gts_pack.all;
library synplify;
use synplify.attributes.all;
 
 
entity cmd_dec is
  port (
        bcast_out : out std_logic_vector(7 downto 0 );
        DoubleErr : out std_ulogic;
        event_num : out std_logic_vector(23 downto 0 );
        MultipleErr : out std_ulogic;
        SingleErr : out std_ulogic;
        outofsync : in std_logic;
        bclk : in std_logic;
        L1A : out std_logic_vector(15 downto 0 );
        msb : in std_logic_vector(7 downto 0 );
        L1A_arrived : out std_logic;
        lreset : in std_logic;
        bcast_strobe : out std_logic;
        CheckOut : out std_logic_vector(0 to 3 );
        reset : out std_logic
        );
 
 
end cmd_dec;
 
 
use work.all;
architecture cmd_dec of cmd_dec is
 
  signal O : std_logic_vector(0 to 3 );
  signal nib : std_logic_vector(0 to 3 );
  signal DataIn : std_logic_vector(0 to 3 );
  signal CheckIn : std_logic_vector(0 to 3 );
  component cmd_dec_ctrl
      port (
            L1A : out std_logic_vector(15 downto 0 );
            reset : out std_logic;
            event_num : out std_logic_vector(23 downto 0 );
            bcast_strobe : out std_logic;
            bcast_out : out std_logic_vector(7 downto 0 );
            L1A_arrived : out std_logic;
            bclk : in std_logic;
            lreset : in std_logic;
            nib : in std_logic_vector(0 to 3 );
            outofsync : in std_logic
            );
  end component;
  component Hamming4
      port (
            DataOut : in std_logic_vector(0 to 3 );
            CheckOut : out std_logic_vector(0 to 3 );
            DataIn : in std_logic_vector(0 to 3 );
            CheckIn : in std_logic_vector(0 to 3 );
            DataCorr : out std_logic_vector(0 to 3 );
            SingleErr : out std_ulogic;
            DoubleErr : out std_ulogic;
            MultipleErr : out std_ulogic
            );
  end component;
 
  -- Start Configuration Specification
  -- ++ for all : cmd_dec_ctrl use entity work.cmd_dec_ctrl(cmd_dec_ctrl);
  -- ++ for all : Hamming4 use entity work.Hamming4(RTL);
  -- End Configuration Specification
 
begin
 
  inst_cmd_dec_ctrl: cmd_dec_ctrl
    port map (
              L1A => L1A(15 downto 0),
              reset => reset,
              event_num => event_num(23 downto 0),
              bcast_strobe => bcast_strobe,
              bcast_out => bcast_out(7 downto 0),
              L1A_arrived => L1A_arrived,
              bclk => bclk,
              lreset => lreset,
              nib => nib(0 to 3),
              outofsync => outofsync
              );
 
  C3: Hamming4
    port map (
              DataOut => O(0 to 3),
              CheckOut => CheckOut(0 to 3),
              DataIn => DataIn(0 to 3),
              CheckIn => CheckIn(0 to 3),
              DataCorr => nib(0 to 3),
              SingleErr => SingleErr,
              DoubleErr => DoubleErr,
              MultipleErr => MultipleErr
              );
 
  DataIn(0 to 3) < = msb(3 downto 0);
  CheckIn(0 to 3) < = msb(7 downto 4);
 
      O(0 to 3) < = (others => '0');
end cmd_dec;
----------------------------------------------------
--  
--  Library Name :  XilinxCoreLib
--  Unit    Name :  C_REG_FD_V7_0
--  Unit    Type :  Text Unit
--  
------------------------------------------------------
-- Copyright(C) 2003 by Xilinx, Inc. All rights reserved.
-- This text/file contains proprietary, confidential
-- information of Xilinx, Inc., is distributed under license
-- from Xilinx, Inc., and may be used, copied and/or
-- disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you
-- a license to use this text/file solely for design, simulation,
-- implementation and creation of design files limited
-- to Xilinx devices or technologies. Use with non-Xilinx
-- devices or technologies is expressly prohibited and
-- immediately terminates your license unless covered by
-- a separate agreement.
--
-- Xilinx is providing this design, code, or information
-- "as is" solely for use in developing programs and
-- solutions for Xilinx devices. By providing this design,
-- code, or information as one possible implementation of
-- this feature, application or standard, Xilinx is making no
-- representation that this implementation is free from any
-- claims of infringement. You are responsible for
-- obtaining any rights you may require for your implementation.
-- Xilinx expressly disclaims any warranty whatsoever with
-- respect to the adequacy of the implementation, including
-- but not limited to any warranties or representations that this
-- implementation is free from claims of infringement, implied
-- warranties of merchantability or fitness for a particular
-- purpose.
--
-- Xilinx products are not intended for use in life support
-- appliances, devices, or systems. Use in such applications are
-- expressly prohibited.
--
-- $Id: c_reg_fd_v7_0.vhd,v 1.3.12.3 2004/10/29 18:47:27 cc Exp $
--
-- Filename - c_reg_fd_v7_0.vhd
-- Author - Xilinx
-- Creation - 21 Sept 1998
--
-- Description - This file contains the behavior for the baseblocks C_REG_FD_V7_0 module

Library IEEE;
Use IEEE.std_logic_1164.all;

Library XilinxCoreLib;
Use XilinxCoreLib.prims_utils_v7_0.all;
use XilinxCoreLib.prims_constants_v7_0.all;

-- bwid bit wide register with asynchronous clear

entity C_REG_FD_V7_0 is
	generic (C_WIDTH 		: integer := 16;
			 C_AINIT_VAL 	: string  := "";
			 C_SINIT_VAL 	: string  := "";
			 C_SYNC_PRIORITY: integer := c_clear;
			 C_SYNC_ENABLE 	: integer := c_override; 
			 C_HAS_CE 		: integer := 0;
			 C_HAS_ACLR 	: integer := 0;
			 C_HAS_ASET 	: integer := 0;
			 C_HAS_AINIT 	: integer := 0;
			 C_HAS_SCLR 	: integer := 0;
			 C_HAS_SSET 	: integer := 0;
			 C_HAS_SINIT 	: integer := 0;
			 C_ENABLE_RLOCS : integer := 1
			 ); 

    port (D : in std_logic_vector(C_WIDTH-1 downto 0) := (others => '0'); -- Input value
		  CLK : in std_logic := '0'; -- Clock
		  CE : in std_logic := '1'; -- Clock Enable
		  ACLR : in std_logic := '0'; -- Asynch clear.
		  ASET : in std_logic := '0'; -- Asynch set.
		  AINIT : in std_logic := '0'; -- Asynch init.
		  SCLR : in std_logic := '0'; -- Synch clear.
		  SSET : in std_logic := '0'; -- Synch set.
		  SINIT : in std_logic := '0'; -- Synch init.
		  Q : out std_logic_vector(C_WIDTH-1 downto 0)); -- Output value
end C_REG_FD_V7_0;



architecture behavioral of C_REG_FD_V7_0 is

	constant timeunit : time := 1 ns;

	signal intQ : std_logic_vector(C_WIDTH-1 downto 0) := (others => 'X');
	-- signals for optional pins...
	signal intCE : std_logic;
	signal intACLR : std_logic;
	signal intASET : std_logic;
	signal intAINIT : std_logic;
	signal intSCLR : std_logic;
	signal intSSET : std_logic;
	signal intSINIT : std_logic;
	signal AIV : std_logic_vector(C_WIDTH-1 downto 0) := str_to_slv_0(C_AINIT_VAL, C_WIDTH);
	signal SIV : std_logic_vector(C_WIDTH-1 downto 0) := str_to_slv_0(C_SINIT_VAL, C_WIDTH);
	
	constant all0s : std_logic_vector(C_WIDTH-1 downto 0) := (others => '0');
	constant all1s : std_logic_vector(C_WIDTH-1 downto 0) := (others => '1');
	constant allXs : std_logic_vector(C_WIDTH-1 downto 0) := (others => 'X');
begin

	-- Deal with optional pins...
	ce1: if C_HAS_CE = 1 generate
		ce1_1 : if ((((C_HAS_ACLR = 1) or (C_HAS_ASET = 1) or (C_HAS_AINIT = 1))
					and ((C_HAS_SCLR = 1) or (C_HAS_SSET = 1) or (C_HAS_SINIT = 1)))
					or ((C_HAS_SCLR = 1) and (C_HAS_SSET = 1) and (C_SYNC_PRIORITY = c_set)))
					and (C_HAS_CE = 1) and (C_SYNC_ENABLE = c_override) generate
				intCE < = CE or intSCLR or intSSET or intSINIT;
		end generate; 
		ce1simple : if (C_HAS_CE = 1) and not(((((C_HAS_ACLR = 1) or (C_HAS_ASET = 1) or (C_HAS_AINIT = 1))
					and ((C_HAS_SCLR = 1) or (C_HAS_SSET = 1) or (C_HAS_SINIT = 1)))
					or ((C_HAS_SCLR = 1) and (C_HAS_SSET = 1) and (C_SYNC_PRIORITY = c_set)))
					and (C_SYNC_ENABLE = c_override)) generate
			intCE < = CE;
		end generate;
	end generate;
	ce0: if not (C_HAS_CE = 1) generate
		intCE < = '1';
	end generate;
	
	aclr1: if C_HAS_ACLR = 1 generate
		intACLR < = ACLR;
	end generate;
	aclr0: if not (C_HAS_ACLR = 1) generate
		intACLR < = '0';
	end generate;
	
	aset1: if C_HAS_ASET = 1 generate
		intASET < = ASET;
	end generate;
	aset0: if not (C_HAS_ASET = 1) generate
		intASET < = '0';
	end generate;
	
	ainit1: if C_HAS_AINIT = 1 generate
		intAINIT < = AINIT;
	end generate;
	ainit0: if not (C_HAS_AINIT = 1) generate
		intAINIT < = '0';
	end generate;
	
	sclr1: if C_HAS_SCLR = 1 generate
		intSCLR < = SCLR;
	end generate;
	sclr0: if not (C_HAS_SCLR = 1) generate
		intSCLR < = '0';
	end generate;
	
	sset1: if C_HAS_SSET = 1 generate
		intSSET < = SSET;
	end generate;
	sset0: if not (C_HAS_SSET = 1) generate
		intSSET < = '0';
	end generate;
	
	sinit1: if C_HAS_SINIT = 1 generate
		intSINIT < = SINIT;
	end generate;
	sinit0: if not (C_HAS_SINIT = 1) generate
		intSINIT < = '0';
	end generate;
	
	
	p1 : process(CLK, intCE, intACLR, intASET, intAINIT, intSCLR, intSSET, intSINIT)
		variable FIRST : boolean := TRUE;
		variable ASYNC_CTRL : boolean := FALSE;
		variable ACTIVE_CLK : std_logic;
		variable SET_OR_CLR : std_logic := '0';
		variable intQtmp : std_logic_vector(C_WIDTH-1 downto 0);
	begin
		
		if FIRST then
			-- Define power-up value
			if C_HAS_ACLR = 1 then
				intQ < = (others => '0');
			elsif C_HAS_ASET = 1 then
				intQ < = (others => '1');
			elsif C_HAS_AINIT = 1 then
				intQ < = AIV;
			elsif (C_HAS_SCLR = 1) then
				intQ < = (others => '0');
			elsif (C_HAS_SSET = 1) then
				intQ < = (others => '1');
			elsif (C_HAS_SINIT = 1) then
				intQ < = SIV;
			else
				intQ < = AIV;
			end if;
			
			if C_SYNC_PRIORITY = 0 then 
				SET_OR_CLR := '0'; -- use SSET
			else -- c_clear
				SET_OR_CLR := '1'; -- use SCLR
			end if;

			
			ACTIVE_CLK := '1';

			FIRST := FALSE;
			
		else -- Not FIRST
		
			intQtmp := intQ;
			
--			for i in 0 to C_WIDTH-1 loop
		
				if intACLR = '1' then -- asynch clear
					intQtmp := all0s;

				elsif intACLR = '0' and intASET = '1' then -- asynch set
					intQtmp := all1s;

				elsif intAINIT = '1' then -- Asynch init, aclr and aset = 0
					intQtmp := AIV;
				
				elsif intACLR = 'X' and intASET /= '0' then -- Undefined!
					intQtmp := allXs;
					
				elsif intACLR'event and intASET'event and intACLR'last_value = '1'
						and intASET'last_value = '1' and intACLR = '0' and intASET = '0' then -- RACE!
					intQtmp := allXs;

				else
					ASYNC_CTRL := FALSE;

					if (CLK'event and CLK'last_value = '0' and CLK = '1') then -- rising edge!
						if ((intCE /= '0' or C_SYNC_ENABLE = 0) and (SET_OR_CLR = '0' and intSSET = 'X' and intSCLR /= '0')) then
							intQtmp := allXs;
							ASYNC_CTRL := TRUE;
						end if;
						if ((intCE /= '0' or C_SYNC_ENABLE = 0) and (SET_OR_CLR = '1' and intSSET /= '0' and intSCLR = 'X')) then
							intQtmp := allXs;
							ASYNC_CTRL := TRUE;
						end if;
						
						if (intCE = '1' and intSCLR /= '1' and intSSET /= '1' and intSINIT /= '1' and ASYNC_CTRL = FALSE) then -- Enabled
							intQtmp := D;
						elsif (intCE = 'X' and intSCLR /= '1' and intSSET /= '1' and intSINIT /= '1' and ASYNC_CTRL = FALSE) then -- possibly enabled
							intQtmp := not((not(intQtmp xor D) or allXs) xor intQtmp);
						end if;
						if (intSINIT = '1' and (intCE = '1' or C_SYNC_ENABLE = 0) and ASYNC_CTRL = FALSE) then -- SINIT
							intQtmp := SIV;
						elsif (intSINIT = '1' and (intCE = 'X' and C_SYNC_ENABLE = 1)) then -- possible init
							intQtmp := not((not(intQtmp xor SIV) or allXs) xor intQtmp);
						elsif (intSINIT = 'X' and (intCE /= '0' or C_SYNC_ENABLE = 0)) then -- possible init
							intQtmp := not((not(intQtmp xor SIV) or allXs) xor intQtmp);
						end if;
						if (intSCLR = '1' and (intCE = '1' or C_SYNC_ENABLE = 0) and (SET_OR_CLR = '1' or intSSET = '0') and ASYNC_CTRL = FALSE) then -- SCLR
							intQtmp := all0s;
						elsif (intSCLR = '1' and (intCE = 'X' and C_SYNC_ENABLE = 1) and (SET_OR_CLR = '1' or intSSET = '0')) then -- possible init
							intQtmp := intQtmp and allXs;
						elsif (intSCLR = 'X' and (intCE /= '0' or C_SYNC_ENABLE = 0) and (SET_OR_CLR = '1' or intSSET = '0')) then -- possible init
							intQtmp := intQtmp and allXs;
						end if;
						if (intSSET = '1' and (intCE = '1' or C_SYNC_ENABLE = 0) and (SET_OR_CLR = '0' or intSCLR = '0') and ASYNC_CTRL = FALSE) then -- SSET
							intQtmp := all1s;
						elsif (intSSET = '1' and (intCE = 'X' and C_SYNC_ENABLE = 1) and (SET_OR_CLR = '0' or intSCLR = '0')) then -- possible init
							intQtmp := intQtmp or allXs;
						elsif (intSSET = 'X' and (intCE /= '0' or C_SYNC_ENABLE = 0) and (SET_OR_CLR = '0' or intSCLR = '0')) then -- possible init
							intQtmp := intQtmp or allXs;
						end if;
					elsif(CLK'event and ((CLK'last_value = '0' and CLK = 'X') or (CLK'last_value = 'X' and CLK = '1'))) then -- possible rising edge
						if ((intCE /= '0' or C_SYNC_ENABLE = 0) and (SET_OR_CLR = '0' and intSSET = 'X' and intSCLR /= '0')) then
							intQtmp := allXs;
						end if;
						if ((intCE /= '0' or C_SYNC_ENABLE = 0) and (SET_OR_CLR = '1' and intSSET /= '0' and intSCLR = 'X')) then
							intQtmp := allXs;
						end if;
						
						if (intCE /= '0' and intSCLR /= '1' and intSSET /= '1' and intSINIT /= '1') then -- Enabled
							intQtmp := not((not(intQtmp xor D) or allXs) xor intQtmp);
						end if;
						if (intSINIT /= '0' and (intCE /= '0' or C_SYNC_ENABLE = 0)) then -- SINIT
							intQtmp := not((not(intQtmp xor SIV) or allXs) xor intQtmp);
						end if;
						if (intSCLR /= '0' and (intCE /= '0' or C_SYNC_ENABLE = 0) and (SET_OR_CLR = '1' or intSSET = '0')) then -- SCLR
							intQtmp := intQtmp and allXs;
						end if;
						if (intSSET /= '0' and (intCE /= '0' or C_SYNC_ENABLE = 0) and (SET_OR_CLR = '0' or intSCLR = '0')) then -- SSET
							intQtmp := intQtmp or allXs;
						end if;
					end if; 

					if intACLR = '0' and intASET = 'X' then -- MAYBE asynch set
--						if intQtmp(i) /= '1' then
--							intQtmp(i) := 'X';
--							ASYNC_CTRL := TRUE;
--						end if;
                                                intQtmp := intQtmp or allXs;
				
					elsif intACLR = 'X' and intASET = '0' then -- MAYBE async clr
--						if intQtmp(i) /= '0' then
--							intQtmp(i) := 'X';
--							ASYNC_CTRL := TRUE;
--						end if;
                                                intQtmp := intQtmp and allXs;

					elsif intAINIT = 'X' then -- MAYBE async init
--						if intQtmp(i) /= AIV(i) then
--							intQtmp(i) := 'X';
--							ASYNC_CTRL := TRUE;
--						end if;
                                                intQtmp := not((not(intQtmp xor AIV) or allXs) xor intQtmp);
					end if;
		
				end if; 	
--			end loop;
			intQ < = intQtmp;
		end if; -- FIRST
		
		
	end process;

	Q < = intQ after timeunit;
	
end behavioral;


----------------------------------------------------
--  
--  Library Name :  XilinxCoreLib
--  Unit    Name :  C_DIST_MEM_V7_1
--  Unit    Type :  Text Unit
--  
------------------------------------------------------
-- Copyright(C) 2004 by Xilinx, Inc. All rights reserved.
-- This text/file contains proprietary, confidential
-- information of Xilinx, Inc., is distributed under license
-- from Xilinx, Inc., and may be used, copied and/or
-- disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you
-- a license to use this text/file solely for design, simulation,
-- implementation and creation of design files limited
-- to Xilinx devices or technologies. Use with non-Xilinx
-- devices or technologies is expressly prohibited and
-- immediately terminates your license unless covered by
-- a separate agreement.
--
-- Xilinx is providing this design, code, or information
-- "as is" solely for use in developing programs and
-- solutions for Xilinx devices. By providing this design,
-- code, or information as one possible implementation of
-- this feature, application or standard, Xilinx is making no
-- representation that this implementation is free from any
-- claims of infringement. You are responsible for
-- obtaining any rights you may require for your implementation.
-- Xilinx expressly disclaims any warranty whatsoever with
-- respect to the adequacy of the implementation, including
-- but not limited to any warranties or representations that this
-- implementation is free from claims of infringement, implied
-- warranties of merchantability or fitness for a particular
-- purpose.
--
-- Xilinx products are not intended for use in life support
-- appliances, devices, or systems. Use in such applications are
-- expressly prohibited.
--
-- This copyright and support notice must be retained as part
-- of this text at all times. (c) Copyright 1995-2004 Xilinx, Inc.
-- All rights reserved.
--
-- $Revision: 1.2.14.3 $ $Date: 2004/10/29 18:48:04 $
-- ************************************************************************

--
--  Description:
--   Distributed RAM Simulation Model
--   VHDL-87 compatable version
--   Also compatable with VHDL-93
--   User cannot generate a Memory Initialization file from the memory
--   contents, unless xilinxcorelib.mem_init_file pack is compiled from
--   either mem_init_file_pack_87.vhd or mem_init_file_pack_93.vhd.
--   Default compilation was mem_init_file_pack.vhd
--   However, this will not be available with Emerald IP, so we shall
--   utilise the mem_init_file_pack_v3_1, which was released with the
--   last version of the sp block memory.  The content of the new package
--   is unchanged, all that has changed is the addition of a version number to
--   the package name.
--

--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.all;
--  
LIBRARY xilinxcorelib;
USE xilinxcorelib.ul_utils.ALL;
USE xilinxcorelib.iputils_mem87.all;
USE xilinxcorelib.prims_constants_V7_0.all;
USE xilinxcorelib.prims_utils_V7_0.all;
--USE xilinxcorelib.c_reg_fd_V7_0_comp.all;
USE work.c_reg_fd_V7_0_comp.all;
--

ENTITY C_DIST_MEM_V7_1 IS
  GENERIC (
            C_ADDR_WIDTH     : integer := 6;
            C_DEFAULT_DATA   : string  := "0";
	    C_DEFAULT_DATA_RADIX : integer := 1;
            C_DEPTH          : integer := 64;
            C_ENABLE_RLOCS   : integer := 1;   -- Unused by the behavioural model
            C_GENERATE_MIF   : integer := 0;   -- Unused by the behavioural model
            C_HAS_CLK        : integer := 1;
            C_HAS_D          : integer := 1;
            C_HAS_DPO        : integer := 0;
            C_HAS_DPRA       : integer := 0;
            C_HAS_I_CE       : integer := 0;
            C_HAS_QDPO       : integer := 0;
            C_HAS_QDPO_CE    : integer := 0;
            C_HAS_QDPO_CLK   : integer := 0;
            C_HAS_QDPO_RST   : integer := 0;    -- RSTB
	    C_HAS_QDPO_SRST	: integer := 0;
            C_HAS_QSPO       : integer := 0;
            C_HAS_QSPO_CE    : integer := 0;
            C_HAS_QSPO_RST   : integer := 0;    --RSTA
	    C_HAS_QSPO_SRST	: integer := 0;
            C_HAS_RD_EN      : integer := 0;
            C_HAS_SPO        : integer := 1;
            C_HAS_SPRA       : integer := 0;
            C_HAS_WE         : integer := 1;
            C_LATENCY    : integer := 0;
            C_MEM_INIT_FILE  : string  := "null.mif";
            C_MEM_TYPE       : integer := c_sp_ram;
            C_MUX_TYPE       : integer := c_lut_based;
            C_QUALIFY_WE     : integer := 0;
            C_QCE_JOINED     : integer := 0;
            C_READ_MIF       : integer := 0;
            C_REG_A_D_INPUTS : integer := 0;
            C_REG_DPRA_INPUT : integer := 0;
            C_SYNC_ENABLE    : integer := 0;
            C_WIDTH          : integer := 16;
	    C_RAM32_FIX      : integer := 0	-- should not be passed in to simulation model
  );
  
  PORT (A        : in  std_logic_vector(C_ADDR_WIDTH-1-(4*C_HAS_SPRA*boolean'pos(C_ADDR_WIDTH>4)) downto 0) := (OTHERS => '0');
        D        : in  std_logic_vector(C_WIDTH-1 downto 0) := (OTHERS => '0');
        DPRA     : in  std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (OTHERS => '0');
        SPRA     : in  std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (OTHERS => '0');
        CLK      : in  std_logic := '0';
        WE       : in  std_logic := '0';
        I_CE     : in  std_logic := '1';
        RD_EN    : in  std_logic := '0';
        QSPO_CE  : in  std_logic := '1';
        QDPO_CE  : in  std_logic := '1';
        QDPO_CLK : in  std_logic := '0';
        QSPO_RST : in std_logic := '0';
        QDPO_RST : in std_logic := '0';
	QSPO_SRST : in std_logic := '0';
	QDPO_SRST : in std_logic := '0';
        SPO      : out std_logic_vector(C_WIDTH-1 downto 0);
        DPO      : out std_logic_vector(C_WIDTH-1 downto 0);
        QSPO     : out std_logic_vector(C_WIDTH-1 downto 0);
        QDPO     : out std_logic_vector(C_WIDTH-1 downto 0)); 
        
END C_DIST_MEM_V7_1;


--
-- behavior describing a parameterized distributed memory
--
ARCHITECTURE behavioral OF C_DIST_MEM_V7_1 IS
--
 -- Address signal connected to memory
 SIGNAL a_int        : STD_LOGIC_VECTOR(C_ADDR_WIDTH-1 DOWNTO 0);
 -- Read Address signal connected to srl16-based memory
 SIGNAL spra_int        : STD_LOGIC_VECTOR(C_ADDR_WIDTH-1 DOWNTO 0);
 -- DP port address signal connected to memory
 SIGNAL dpra_int     : STD_LOGIC_VECTOR(C_ADDR_WIDTH-1 DOWNTO 0);
 -- Input data signal connected to memory
 SIGNAL d_int        : STD_LOGIC_VECTOR(C_WIDTH-1 DOWNTO 0) := (OTHERS => 'X');
 -- DP output register clock
 SIGNAL doclk        : STD_LOGIC := '0';
 -- Input data/address/WE register Clock Enable
 SIGNAL ice          : STD_LOGIC := '1';
 -- Special address register Clock Enable for ROMs
 SIGNAL a_reg_ice    : STD_LOGIC := '1';
 -- DP read address port register clock enable
-- SIGNAL dpra_ce      : STD_LOGIC := '1';
 -- WE signal connected to memory
 SIGNAL we_int       : STD_LOGIC := '1';
 -- Clock enable for the WE register
 SIGNAL wece         : STD_LOGIC := '1';
 -- Read Enable signal connected to BUFT-type output mux
 SIGNAL re_int       : STD_LOGIC := '1';
 -- unregistered version of qspo_ce
 SIGNAL qspo_ce_int  : STD_LOGIC := '1'; 
 -- possibly registered version of qspo_ce
 SIGNAL qspo_ce_reg  : STD_LOGIC := '1'; 
 -- unregistered version of qdpo_ce
 SIGNAL qdpo_ce_int  : STD_LOGIC := '1'; 
 -- possibly registered version of qdpo_ce
 SIGNAL qdpo_ce_reg  : STD_LOGIC := '1'; 
 -- possibly single port registered output reset
 SIGNAL qspo_rst_int : STD_LOGIC := '1';
 -- possibly dual port registered output reset
 SIGNAL qdpo_rst_int : STD_LOGIC := '1';
 -- possibly single port registered output sync reset
 SIGNAL qspo_srst_int : STD_LOGIC := '1';
 -- possibly dual port registered output sync reset
 SIGNAL qdpo_srst_int : STD_LOGIC := '1';
 -- Direct SP output from memory
 SIGNAL spo_async    : STD_LOGIC_VECTOR(C_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
 -- Direct DP output from memory
 SIGNAL dpo_async    : STD_LOGIC_VECTOR(C_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
 -- Possibly pipelined SP output from memory
 SIGNAL spo_reg      : STD_LOGIC_VECTOR(C_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
 -- Possibly pipelined DP output from memory
 SIGNAL dpo_reg      : STD_LOGIC_VECTOR(C_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
--
 SIGNAL spo_buft     : STD_LOGIC_VECTOR(C_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
 SIGNAL dpo_buft     : STD_LOGIC_VECTOR(C_WIDTH-1 DOWNTO 0) := (OTHERS => '0');

 FUNCTION getRadix(C_DEFAULT_DATA_RADIX, C_MEM_INIT_RADIX : INTEGER) RETURN INTEGER IS
 BEGIN
    IF (C_DEFAULT_DATA_RADIX = 1) THEN
        RETURN C_MEM_INIT_RADIX;
    ELSE
        RETURN C_DEFAULT_DATA_RADIX;
    END IF;
 END getRadix;
--
 
 CONSTANT radix : INTEGER := C_DEFAULT_DATA_RADIX;
 CONSTANT pipe_stages : INTEGER := C_LATENCY-C_REG_A_D_INPUTS;
 CONSTANT dpo_pipe_stages : INTEGER := pipe_stages+C_HAS_QDPO-C_HAS_QSPO;
 -- Pipeline signals
 type ST_PIPE_SIGNAL is array (0 to pipe_stages+1) of STD_LOGIC_VECTOR(C_WIDTH-1 DOWNTO 0);
 type DT_PIPE_SIGNAL is array (0 to dpo_pipe_stages+1) of STD_LOGIC_VECTOR(C_WIDTH-1 DOWNTO 0);
 SIGNAL spo_pipe 	 : ST_PIPE_SIGNAL := (others => (others => '0'));
 SIGNAL dpo_pipe 	 : DT_PIPE_SIGNAL := (others => (others => '0'));
--
BEGIN
--
 -- Optional I_CE signal
 ice1 : IF (C_HAS_I_CE = 1) GENERATE
   ice < = I_CE;
 END GENERATE;
 ice0 : IF (C_HAS_I_CE = 0) GENERATE
   ice < = '1';
 END GENERATE;
 
 -- Different address clock enable for ROM as for other mems
 aregice1 : IF (C_MEM_TYPE = c_rom) GENERATE
   a_reg_ice < = qspo_ce_int;
 END GENERATE;
 aregice0 : IF (C_MEM_TYPE /= c_rom) GENERATE
   a_reg_ice < = ice;
 END GENERATE;
 
 -- Option CE for optional WE register
 wece1 : IF (C_HAS_WE = 1 AND C_REG_A_D_INPUTS = 1 AND C_QUALIFY_WE = 1) GENERATE
   wece < = ice;
 END GENERATE;
 wece0 : IF (C_HAS_WE = 1 AND C_REG_A_D_INPUTS = 1 AND C_QUALIFY_WE = 0) GENERATE
   wece < = '1';
 END GENERATE;
 
 -- Optional separate DP-CLK
 qdpoclk1: IF (C_HAS_QDPO_CLK = 1) GENERATE
   doclk < = QDPO_CLK;
 END GENERATE;
 -- Otherwise use common clock
 qdpoclk0: IF (C_HAS_QDPO_CLK = 0) GENERATE
   doclk < = CLK;
 END GENERATE;

 -- Optional CE signals
 qspoce1 : IF (C_HAS_QSPO_CE = 1) GENERATE
   qspo_ce_int < = QSPO_CE;
 END GENERATE;
 qspoce0 : IF (C_HAS_QSPO_CE = 0) GENERATE
   qspo_ce_int < = '1';
 END GENERATE;

 qdpoce1 : IF (C_HAS_QDPO_CE = 1 AND C_QCE_JOINED = 0) GENERATE
   qdpo_ce_int < = QDPO_CE;
 END GENERATE;
 qdpoce01 : IF (C_HAS_QSPO_CE = 1 AND C_QCE_JOINED = 1) GENERATE
   qdpo_ce_int < = qspo_ce_int;
 END GENERATE;
 qdpoce0 : IF (C_HAS_QDPO_CE = 0 AND C_HAS_QSPO_CE = 1 AND C_MEM_TYPE = c_srl16) GENERATE
   qdpo_ce_int < = qspo_ce_int;
 END GENERATE;
 qdpoce00 : IF (C_HAS_QDPO_CE = 0 AND NOT (C_HAS_QSPO_CE = 1 AND C_MEM_TYPE = c_srl16)) GENERATE
   qdpo_ce_int < = '1';
 END GENERATE;
 
 -- Optional registered output reset signals
 qsporst1 : IF (C_HAS_QSPO = 1 AND C_HAS_QSPO_RST = 1) GENERATE
    qspo_rst_int < = QSPO_RST;
 END GENERATE;
 qsporst0 : IF (NOT(C_HAS_QSPO = 1 AND C_HAS_QSPO_RST = 1)) GENERATE
    qspo_rst_int < = '0';
 END GENERATE;
 
 qdporst1 : IF (C_HAS_QDPO = 1 AND C_HAS_QDPO_RST = 1) GENERATE
    qdpo_rst_int < = QDPO_RST;
 END GENERATE;
 qdporst0 : IF (NOT(C_HAS_QDPO = 1 AND C_HAS_QDPO_RST = 1)) GENERATE
    qdpo_rst_int < = '0';
 END GENERATE;
 
 qsposrst1 : IF (C_HAS_QSPO = 1 AND C_HAS_QSPO_SRST = 1) GENERATE
    qspo_srst_int < = QSPO_SRST;
 END GENERATE;
 qsposrst0 : IF (NOT(C_HAS_QSPO = 1 AND C_HAS_QSPO_SRST = 1)) GENERATE
    qspo_srst_int < = '0';
 END GENERATE;
 
 qdposrst1 : IF (C_HAS_QDPO = 1 AND C_HAS_QDPO_SRST = 1) GENERATE
    qdpo_srst_int < = QDPO_SRST;
 END GENERATE;
 qdposrst0 : IF (NOT(C_HAS_QDPO = 1 AND C_HAS_QDPO_SRST = 1)) GENERATE
    qdpo_srst_int < = '0';
 END GENERATE;
 
 -- Optional registers on SP address and on optional data/we/qspo_ce signals

 -- No Registers! 
 a_d_reg0: IF (C_REG_A_D_INPUTS = 0) GENERATE

   qspo1 : IF (C_HAS_QSPO_CE = 1) GENERATE
     qspo_ce_reg < = qspo_ce_int;
   END GENERATE;
   qspo0 : IF (C_HAS_QSPO_CE = 0) GENERATE
     qspo_ce_reg < = '1';
   END GENERATE;

   mem1 : IF (C_MEM_TYPE /= c_srl16) GENERATE
     a_int < = A;
	 spra_int < = A;
   END GENERATE;
   mem2 : IF (C_MEM_TYPE = c_srl16) GENERATE
	   awgt4 : IF(C_ADDR_WIDTH > 4) GENERATE
	   	 a_int(C_ADDR_WIDTH-1 downto 4) < = A(C_ADDR_WIDTH-5 downto 0);
	   END GENERATE;
   	   a_int(3 downto 0) < = (others => '0');
	   
	   spra0 : IF (C_HAS_SPRA = 0) GENERATE
	   -- This is NOT possible!!
	     spra_int < = (others => 'X');
	   END GENERATE;
	   spra1 : IF (C_HAS_SPRA = 1) GENERATE
	     spra_int < = SPRA;
	   END GENERATE;	   
   END GENERATE;

   we1 : IF (C_HAS_WE = 1) GENERATE
     we_int < = we;
   END GENERATE;
   we0 : IF (C_HAS_WE = 0) GENERATE
     we_int < = '1';
   END GENERATE;

   re1 : IF (C_HAS_RD_EN = 1) GENERATE
     re_int < = RD_EN;
   END GENERATE;
   re0 : IF (C_HAS_RD_EN = 0) GENERATE
     re_int < = '1';
   END GENERATE;

   d1 : IF (C_HAS_D = 1) GENERATE
     d_int < = D;
   END GENERATE;
   d0 : IF (C_HAS_D = 0) GENERATE
     d_int < = (others => 'X');
   END GENERATE;        

 END GENERATE;
 
 -- There ARE Registers!
 a_d_reg1: IF (C_REG_A_D_INPUTS = 1) GENERATE

   qspo1 : IF (C_HAS_QSPO_CE = 1) GENERATE
     qspo1_reg : C_REG_FD_V7_0 generic map(C_WIDTH => 1,
    							  		   C_HAS_CE => 0)
    					   port map(D(0) => qspo_ce_int,
    								CLK => CLK,
    								Q(0) => qspo_ce_reg);
   END GENERATE;
   qspo0 : IF (C_HAS_QSPO_CE = 0) GENERATE
     qspo_ce_reg < = '1';
   END GENERATE;

   mem1 : IF (C_MEM_TYPE /= c_srl16) GENERATE
     a_reg : 	 C_REG_FD_V7_0 generic map(C_WIDTH => C_ADDR_WIDTH,
     									   C_HAS_CE => 1)
								port map(D => A,
										 CLK => CLK,
										 CE => a_reg_ice,
										 Q => a_int);
	 spra_int < = a_int;
   END GENERATE;
   mem2 : IF (C_MEM_TYPE = c_srl16) GENERATE
     awgt4 : IF (C_ADDR_WIDTH > 4) GENERATE
     	a_reg : 	 C_REG_FD_V7_0 generic map(C_WIDTH => C_ADDR_WIDTH-4,
     										   C_HAS_CE => 1)
								port map(D => A(C_ADDR_WIDTH-5 downto 0),
										 CLK => CLK,
										 CE => a_reg_ice,
										 Q => a_int(C_ADDR_WIDTH-1 downto 4));
	 END GENERATE;
--     spra0 : IF (C_HAS_SPRA = 0) GENERATE
   	   a_int(3 downto 0) < = (others => '0');
--	 END GENERATE;
	 spra1 : IF (C_HAS_SPRA = 1) GENERATE
       spra_reg : C_REG_FD_V7_0 generic map(C_WIDTH => C_ADDR_WIDTH,
     									    C_HAS_CE => 1)
								port map(D => SPRA,
										 CLK => CLK,
										 CE => qspo_ce_int,
										 Q => spra_int);
	 END GENERATE;
   END GENERATE;
						
   we1 : IF (C_HAS_WE = 1) GENERATE
     we_reg : C_REG_FD_V7_0 generic map(C_WIDTH => 1,
   									    C_HAS_CE => 1)
								port map(D(0) => WE,
										 CLK => CLK,
										 CE => wece,
										 Q(0) => we_int);
   END GENERATE;
   we0 : IF (C_HAS_WE = 0) GENERATE
     we_int < = '1';
   END GENERATE;

   re1 : IF (C_HAS_RD_EN = 1) GENERATE
     re_reg : C_REG_FD_V7_0 generic map(C_WIDTH => 1,
   									    C_HAS_CE => 0)
								port map(D(0) => RD_EN,
										 CLK => CLK,
--										 CE => qspo_ce_int,
										 Q(0) => re_int);
   END GENERATE;
   re0 : IF (C_HAS_RD_EN = 0) GENERATE
     re_int < = '1';
   END GENERATE;                                              

   d1 : IF (C_HAS_D = 1) GENERATE
     d_reg : 	 C_REG_FD_V7_0 generic map(C_WIDTH => C_WIDTH,
     									   C_HAS_CE => 1)
								port map(D => D,
										 CLK => CLK,
										 CE => ice,
										 Q => d_int);
   END GENERATE;
   d0 : IF (C_HAS_D = 0) GENERATE
     d_int < = (OTHERS => 'X');
   END GENERATE;
						
 END GENERATE;

 -- Optional DP Read Address and QDPO_CE registers
 
 -- No Registers!
 dpra_reg0: IF (C_REG_DPRA_INPUT = 0) GENERATE

   dpra1 : IF (C_HAS_DPRA = 1) GENERATE
     dpra_int < = DPRA;
   END GENERATE;
   dpra0 : IF (C_HAS_DPRA = 0) GENERATE
     dpra_int < = (OTHERS => 'X');
   END GENERATE;

   qdpo1 : IF (C_HAS_QDPO_CE = 1) GENERATE
     qdpo_ce_reg < = qdpo_ce_int;
   END GENERATE;
   qdpo0 : IF (C_HAS_QDPO_CE = 0 AND C_QCE_JOINED = 1) GENERATE
     qdpo_ce_reg < = qdpo_ce_int;
   END GENERATE;
   qdpo00 : IF (C_HAS_QDPO_CE = 0 AND C_QCE_JOINED = 0) GENERATE
     qdpo_ce_reg < = '1';
   END GENERATE;
   
 END GENERATE;

 -- There ARE Registers!
 dpra_reg1: IF (C_REG_DPRA_INPUT = 1) GENERATE

   dpra1 : IF (C_HAS_DPRA = 1) GENERATE
      dpra_reg : C_REG_FD_V7_0 generic map(C_WIDTH => C_ADDR_WIDTH,
    							  		   C_HAS_CE => 1)
    					   port map(D => DPRA,
    								CLK => doclk,
									CE => qdpo_ce_int,
    								Q => dpra_int);

   END GENERATE;
   dpra0 : IF (C_HAS_DPRA = 0) GENERATE
     dpra_int < = (OTHERS => 'X');
   END GENERATE;

   qdpo1 : IF (C_HAS_QDPO_CE = 1 or (C_QCE_JOINED = 1 AND C_REG_A_D_INPUTS = 0)) GENERATE
     qdpo1_reg : C_REG_FD_V7_0 generic map(C_WIDTH => 1,
    							  		   C_HAS_CE => 0)
    					   port map(D(0) => qdpo_ce_int,
    								CLK => doclk,
    								Q(0) => qdpo_ce_reg);

   END GENERATE;
   qdpo0 : IF (C_HAS_QDPO_CE = 0 AND C_REG_A_D_INPUTS = 1 AND C_HAS_QSPO_CE = 1 AND (C_MEM_TYPE = c_srl16 OR C_QCE_JOINED = 1)) GENERATE
     qdpo_ce_reg < = qspo_ce_reg;
   END GENERATE;
   qdpo00 : IF (C_HAS_QDPO_CE = 0 AND not(C_HAS_QSPO_CE = 1 AND (C_MEM_TYPE = c_srl16 OR C_QCE_JOINED = 1))) GENERATE
     qdpo_ce_reg < = '1';
   END GENERATE;
   
 END GENERATE;
 
 -- Optional Async Single Port Output
 soexc: IF (C_HAS_SPO = 0) GENERATE
   SPO < = (OTHERS => 'X');
 END GENERATE;
 soinc: IF (C_HAS_SPO = 1 AND C_MUX_TYPE = c_lut_based) GENERATE
   SPO < = spo_async;
 END GENERATE;
 soinc_buft : IF (C_HAS_SPO = 1 AND C_MUX_TYPE /= c_lut_based) GENERATE
   SPO < = spo_reg;
 END GENERATE;
 
 -- Optional Async Dual Port Output
 -- Only allowed for Dual port modules with lut based mux
 doexc: IF (C_HAS_DPO = 0 OR 
            C_MEM_TYPE /= c_dp_ram) GENERATE
   DPO < = (OTHERS => 'X');
 END GENERATE;
 doinc: IF (C_HAS_DPO = 1 AND
            C_MEM_TYPE = c_dp_ram AND C_MUX_TYPE = c_lut_based) GENERATE
   DPO < = dpo_async;
 END GENERATE;
 doinc_buft : IF (C_HAS_DPO = 1 AND C_MEM_TYPE = c_dp_ram AND C_MUX_TYPE /= c_lut_based) GENERATE
   DPO < = dpo_reg;
 END GENERATE;

 -- Optional registered outputs
 qspoexc: IF (C_HAS_QSPO = 0) GENERATE
   QSPO < = (OTHERS => 'X');
 END GENERATE;
 qdpoexc: IF (C_HAS_QDPO = 0) GENERATE
   QDPO < = (OTHERS => 'X');
 END GENERATE;
 
 -- Optional Pipe stages
 sporeg0: IF(pipe_stages <  2 AND C_MUX_TYPE = c_lut_based) GENERATE
 	spo_reg < = spo_async;
 END GENERATE;
 sporeg1: IF(pipe_stages > 1 AND C_MUX_TYPE = c_lut_based) GENERATE
   qspoinc: IF (C_HAS_QSPO = 1) GENERATE
     spo_pipe(0) < = spo_async; -- Input to pipeline
	 spo_reg < = spo_pipe(pipe_stages-1); -- Output from pipeline
     pipe_s: FOR i in 0 to pipe_stages - 2 GENERATE
	   pipe_s_reg : C_REG_FD_V7_0
             GENERIC MAP ( C_WIDTH => C_WIDTH,
                           C_HAS_CE => 1) 
             PORT MAP ( D => spo_pipe(i),
                        CLK => CLK,
                        CE => qspo_ce_reg,
                        Q => spo_pipe(i+1));
	 END GENERATE;
   END GENERATE;
 END GENERATE;
 sporeg2 : IF (pipe_stages = 0 AND C_MUX_TYPE /= c_lut_based) GENERATE
    spo_reg < = spo_buft;
 END GENERATE;
 sporeg3 : IF (pipe_stages = 1 AND C_MUX_TYPE /= c_lut_based) GENERATE
    pipe_s_reg : C_REG_FD_V7_0
         GENERIC MAP ( C_WIDTH => C_WIDTH,
                       C_HAS_CE => 0) 
         PORT MAP ( D => spo_buft,
                    CLK => CLK,
                    Q => spo_reg);
 END GENERATE;
 sporeg4 : IF (C_MUX_TYPE /= c_lut_based) GENERATE
    spo_buft < = spo_async after 1 ns;
 END GENERATE;

 dporeg0: IF(dpo_pipe_stages <  2 AND C_MUX_TYPE = c_lut_based) GENERATE
 	dpo_reg < = dpo_async;
 END GENERATE;
 dporeg1: IF(dpo_pipe_stages > 1 AND C_MUX_TYPE = c_lut_based) GENERATE
   qdpoinc: IF (C_HAS_QDPO = 1) GENERATE
     dpo_pipe(0) < = dpo_async; -- Input to pipeline
	 dpo_reg < = dpo_pipe(dpo_pipe_stages-1); -- Output from pipeline
     pipe_d: FOR i in 0 to dpo_pipe_stages - 2 GENERATE
	   pipe_d_reg : C_REG_FD_V7_0
             GENERIC MAP ( C_WIDTH => C_WIDTH,
                           C_HAS_CE => 1) 
             PORT MAP ( D => dpo_pipe(i),
                        CLK => doclk,
                        CE => qdpo_ce_reg,
                        Q => dpo_pipe(i+1));
     END GENERATE;
   END GENERATE;
 END GENERATE;
 dporeg2 : IF (pipe_stages = 0 AND C_MUX_TYPE /= c_lut_based) GENERATE
    dpo_reg < = dpo_buft;
 END GENERATE;
 dporeg3 : IF (pipe_stages = 1 AND C_MUX_TYPE /= c_lut_based) GENERATE
    pipe_d_reg : C_REG_FD_V7_0
         GENERIC MAP ( C_WIDTH => C_WIDTH,
                       C_HAS_CE => 0) 
         PORT MAP ( D => dpo_buft,
                    CLK => doclk,
                    Q => dpo_reg);
 END GENERATE;
 dporeg4 : IF (C_MUX_TYPE /= c_lut_based) GENERATE
    dpo_buft < = dpo_async after 1 ns;
 END GENERATE;
 	
 
 -- Optional Output register
 oreginc: IF (pipe_stages >= 0 OR dpo_pipe_stages >= 0) GENERATE
   qspoinc: IF (C_HAS_QSPO = 1) GENERATE
     pipe_s: C_REG_FD_V7_0
             GENERIC MAP ( C_WIDTH => C_WIDTH,
                           C_HAS_ACLR => C_HAS_QSPO_RST,
                           C_HAS_SCLR => C_HAS_QSPO_SRST,
                           C_HAS_CE => 1,
                           C_SYNC_ENABLE => C_SYNC_ENABLE) 
             PORT MAP ( D => spo_reg,
                        CLK => CLK,
                        CE => qspo_ce_reg,
                        ACLR => QSPO_RST_INT,
			SCLR => QSPO_SRST_INT,
                        Q => QSPO);
   END GENERATE;
   --Dual Port
   dp: IF (C_MEM_TYPE = c_dp_ram) GENERATE
     qdpoinc: IF (C_HAS_QDPO = 1) GENERATE
       pipe_d: C_REG_FD_V7_0
               GENERIC MAP ( C_WIDTH => C_WIDTH,
                           C_HAS_ACLR => C_HAS_QDPO_RST,
                           C_HAS_SCLR => C_HAS_QDPO_SRST,
                             C_HAS_CE => 1,
                             C_SYNC_ENABLE => C_SYNC_ENABLE) 
               PORT MAP ( D => dpo_reg,
                          CLK => doclk,
                          CE => qdpo_ce_reg,
                        ACLR => QDPO_RST_INT,
			SCLR => QDPO_SRST_INT,
                          Q => QDPO);
     END GENERATE;
   END GENERATE;
 END GENERATE;
 
-- Core Memory process
 PROCESS (CLK, a_int, we_int, spra_int, dpra_int, d_int, re_int)
--   
   CONSTANT mem_bits   : INTEGER := C_DEPTH * C_WIDTH;
   VARIABLE memdvect   : STD_LOGIC_VECTOR(mem_bits-1 DOWNTO 0);
   VARIABLE bits_good  : BOOLEAN;
   VARIABLE lineno     : INTEGER := 0;
   VARIABLE offset     : INTEGER := 0;
   VARIABLE def_data   : STD_LOGIC_VECTOR(C_WIDTH-1 DOWNTO 0);
   VARIABLE startup    : BOOLEAN := TRUE;
   VARIABLE spo_tmp    : STD_LOGIC_VECTOR(C_WIDTH-1 DOWNTO 0);
   VARIABLE dpo_tmp    : STD_LOGIC_VECTOR(C_WIDTH-1 DOWNTO 0);
   VARIABLE srl_start  : INTEGER := 0;
   VARIABLE srl_end    : INTEGER := 0;
   variable a_int_var  : std_logic_vector(0 to c_addr_width-1);
--		

   FUNCTION add_std_logic_vec( arg1, arg2 : STD_LOGIC_VECTOR; size : INTEGER ) RETURN STD_LOGIC_VECTOR IS
     VARIABLE S   : STD_LOGIC_VECTOR(size-1 DOWNTO 0) := (OTHERS=>'0');
     VARIABLE C   : STD_LOGIC_VECTOR(size DOWNTO 0) := (OTHERS=>'0');
     VARIABLE A   : STD_LOGIC;
     VARIABLE B   : STD_LOGIC;
   BEGIN
   	 FOR i IN 0 TO size-1 LOOP
       IF( i <  arg1'LENGTH ) THEN
         A := arg1(i);
       ELSE
         A := '0';
       END IF;
       IF( i <  arg2'LENGTH ) THEN
         B := arg2(i);
       ELSE
         B := '0';
       END IF;
       S(i)   := A XOR B;
       C(i+1) := (A AND B) OR (S(i) AND C(i));
       S(i)   := S(i) XOR C(i);
     END LOOP;
     RETURN S;
   END add_std_logic_vec;
-- 
   FUNCTION mul_std_logic_vec( arg1, arg2 : STD_LOGIC_VECTOR; size : INTEGER ) RETURN STD_LOGIC_VECTOR IS
     VARIABLE M   : STD_LOGIC_VECTOR(size-1 DOWNTO 0) := (OTHERS=>'0');
     VARIABLE A   : STD_LOGIC_VECTOR(size-1 DOWNTO 0);
   BEGIN
     FOR i IN 0 TO arg2'LENGTH-1 LOOP
       IF arg2(i) = '1' THEN
         A := (OTHERS=>'0');
         FOR j IN 0 TO arg1'LENGTH-1 LOOP
           IF( i+j <  size ) THEN
             A(i+j) := arg1(j);
           END IF;
         END LOOP;
         M := add_std_logic_vec( M, A, size );
       END IF;
     END LOOP;
     RETURN M;
   END mul_std_logic_vec;
--
   FUNCTION decstr_to_std_logic_vec( arg1 : STRING; size : INTEGER ) RETURN STD_LOGIC_VECTOR IS
     VARIABLE RESULT : STD_LOGIC_VECTOR(size-1 DOWNTO 0):= (OTHERS=>'0');
     VARIABLE BIN    : STD_LOGIC_VECTOR(3 DOWNTO 0);
     CONSTANT TEN    : STD_LOGIC_VECTOR(3 DOWNTO 0) := (3=>'1', 1=>'1', OTHERS=>'0');
     VARIABLE MULT10 : STD_LOGIC_VECTOR(size-1 DOWNTO 0) := std_logic_vector(to_unsigned(1, size));
     VARIABLE MULT   : STD_LOGIC_VECTOR(size-1 DOWNTO 0);
   BEGIN 
     FOR i IN arg1'REVERSE_RANGE LOOP
       CASE arg1(i) IS
         WHEN '0' => BIN := (OTHERS=>'0');
         WHEN '1' => BIN := (0=>'1', OTHERS=>'0');
         WHEN '2' => BIN := (1=>'1', OTHERS=>'0');
         WHEN '3' => BIN := (0=>'1', 1=>'1', OTHERS=>'0');
         WHEN '4' => BIN := (2=>'1', OTHERS=>'0');
         WHEN '5' => BIN := (0=>'1', 2=>'1', OTHERS=>'0');
         WHEN '6' => BIN := (1=>'1', 2=>'1', OTHERS=>'0');
         WHEN '7' => BIN := (3=>'0', OTHERS=>'1');
         WHEN '8' => BIN := (3=>'1', OTHERS=>'0');
         WHEN '9' => BIN := (0=>'1', 3=>'1', OTHERS=>'0');
         WHEN OTHERS =>
           ASSERT FALSE 
             REPORT "NOT A DECIMAL CHARACTER" SEVERITY ERROR;
           RESULT := (OTHERS=>'X');
           RETURN RESULT;
       END CASE;
       MULT := mul_std_logic_vec( MULT10, BIN, size);
       RESULT := add_std_logic_vec( RESULT, MULT, size);
       MULT10 := mul_std_logic_vec( MULT10, TEN, size ); 
     END LOOP;
     RETURN RESULT;
   END decstr_to_std_logic_vec;
--
   FUNCTION binstr_to_std_logic_vec( arg1 : STRING; size : INTEGER ) RETURN STD_LOGIC_VECTOR IS
     VARIABLE RESULT : STD_LOGIC_VECTOR(size-1 DOWNTO 0):= (OTHERS=>'0');
     VARIABLE INDEX : INTEGER := 0;
   BEGIN
     FOR i IN arg1'REVERSE_RANGE LOOP
       CASE arg1(i) IS
         WHEN '0' => RESULT(INDEX) := '0';
         WHEN '1' => RESULT(INDEX) := '1';
         WHEN OTHERS =>
           ASSERT FALSE
             REPORT "NOT A BINARY CHARACTER" SEVERITY ERROR;
           RESULT(INDEX) := 'X';
       END CASE;
       INDEX := INDEX + 1;
     END LOOP;
     RETURN RESULT;
   END binstr_to_std_logic_vec; 
--
   FUNCTION hexstr_to_std_logic_vec( arg1 : STRING; size : INTEGER ) RETURN STD_LOGIC_VECTOR IS
     VARIABLE RESULT : STD_LOGIC_VECTOR(size-1 DOWNTO 0):= (OTHERS=> '0');
     VARIABLE BIN : STD_LOGIC_VECTOR(3 DOWNTO 0);
     VARIABLE INDEX : INTEGER := 0;
   BEGIN
     FOR i IN arg1'REVERSE_RANGE LOOP
       CASE arg1(i) IS
         WHEN '0' => BIN := (OTHERS=>'0');
         WHEN '1' => BIN := (0=>'1', OTHERS=>'0');
         WHEN '2' => BIN := (1=>'1', OTHERS=>'0');
         WHEN '3' => BIN := (0=>'1', 1=>'1', OTHERS=>'0');
         WHEN '4' => BIN := (2=>'1', OTHERS=>'0');
         WHEN '5' => BIN := (0=>'1', 2=>'1', OTHERS=>'0');
         WHEN '6' => BIN := (1=>'1', 2=>'1', OTHERS=>'0');
         WHEN '7' => BIN := (3=>'0', OTHERS=>'1');
         WHEN '8' => BIN := (3=>'1', OTHERS=>'0');
         WHEN '9' => BIN := (0=>'1', 3=>'1', OTHERS=>'0');
         WHEN 'A' => BIN := (0=>'0', 2=>'0', OTHERS=>'1');
         WHEN 'a' => BIN := (0=>'0', 2=>'0', OTHERS=>'1');
         WHEN 'B' => BIN := (2=>'0', OTHERS=>'1');
         WHEN 'b' => BIN := (2=>'0', OTHERS=>'1');
         WHEN 'C' => BIN := (0=>'0', 1=>'0', OTHERS=>'1');
         WHEN 'c' => BIN := (0=>'0', 1=>'0', OTHERS=>'1');
         WHEN 'D' => BIN := (1=>'0', OTHERS=>'1');
         WHEN 'd' => BIN := (1=>'0', OTHERS=>'1');
         WHEN 'E' => BIN := (0=>'0', OTHERS=>'1');
         WHEN 'e' => BIN := (0=>'0', OTHERS=>'1');
         WHEN 'F' => BIN := (OTHERS=>'1');
         WHEN 'f' => BIN := (OTHERS=>'1');
         WHEN OTHERS =>
           ASSERT FALSE
             REPORT "NOT A HEX CHARACTER" SEVERITY ERROR;
           FOR j IN 0 TO 3 LOOP
               BIN(j) := 'X';
           END LOOP;
       END CASE;
       FOR j IN 0 TO 3 LOOP
         IF (INDEX*4)+j <  size THEN
           RESULT((INDEX*4)+j) := BIN(j);
         END IF;
       END LOOP;
       INDEX := INDEX + 1;
     END LOOP;
     RETURN RESULT;	
   END hexstr_to_std_logic_vec;
--
 BEGIN
 
 -- Startup section reads and/or writes mif file if necessary.
 
   IF (startup) THEN
     def_data(C_WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
     CASE radix IS
       WHEN	 3 =>
         def_data := decstr_to_std_logic_vec(C_DEFAULT_DATA, C_WIDTH);
       WHEN      2 => 
         def_data := binstr_to_std_logic_vec(C_DEFAULT_DATA, C_WIDTH);
       WHEN      1 => 
         def_data := hexstr_to_std_logic_vec(C_DEFAULT_DATA, C_WIDTH);
       WHEN OTHERS =>  
         ASSERT FALSE
           REPORT "BAD DATA RADIX" SEVERITY ERROR;
     END CASE;

     IF( C_READ_MIF = 1 ) THEN
       read_meminit_file(C_MEM_INIT_FILE, C_DEPTH, C_WIDTH, memdvect, lineno);
     END IF;
     offset := lineno*C_WIDTH;
     WHILE (lineno <  C_DEPTH) LOOP
       FOR i IN 0 TO C_WIDTH-1 LOOP
         memdvect(offset+i) := def_data(i);
       END LOOP;
       lineno := lineno+1;
       offset := offset+C_WIDTH;
     END LOOP;
     spo_tmp := (OTHERS => '0');
     dpo_tmp := (OTHERS => '0');
	 
     -- writing MIF no longer supported
     
     --IF (C_GENERATE_MIF = 1) THEN 
       --write_meminit_file(C_MEM_INIT_FILE, C_DEPTH, C_WIDTH, memdvect, 0);
     --END IF;
	 
     startup := FALSE;
   ELSE -- Normal operation 
   
	-- a_int is rearranged to deal with Mti 5.6c dealings with unconstrained arrays
	for i in 0 to c_addr_width-1 loop
	   a_int_var(i) := a_int(i);
	end loop;
     -- Deal with good rising CLK edge...
	IF(((CLK'event AND rat(CLK) = '1' AND rat(CLK'LAST_VALUE) = '0') OR C_HAS_CLK = 0) 
		 AND C_MEM_TYPE /= c_rom) THEN

     IF (anyX(a_int) OR std_logic_vector_2_posint(a_int) <  C_DEPTH) THEN
       IF (rat(we_int) = 'X') THEN
         ASSERT FALSE
           REPORT "Memory Hazard: Write enable is not defined at the active clock edge."
           SEVERITY WARNING;      
         IF (anyX(a_int)) THEN
           memdvect := (OTHERS => 'X');
         ELSE
           offset := std_logic_vector_2_posint(a_int)*C_WIDTH;
           IF (C_MEM_TYPE = c_srl16) THEN -- Shift the 'X' data into the SRL16s
		     IF (C_ADDR_WIDTH > 4) THEN
		       srl_start := std_logic_vector_2_posint(a_int);
			 ELSE 
			   srl_start := 0;
			 END IF;
			 srl_end := srl_start + 16;
			 IF srl_end > C_DEPTH THEN
			 	srl_end := C_DEPTH;
			 END IF;
             FOR i IN (srl_end*C_WIDTH)-1 DOWNTO ((srl_start+1)*C_WIDTH) LOOP
               	IF memdvect(i) /= memdvect(i-C_WIDTH) THEN
			   		memdvect(i) := 'X';
			 	END IF;
             END LOOP;
			 FOR i in ((srl_start+1)*C_WIDTH)-1 DOWNTO (srl_start*C_WIDTH) LOOP
			 	IF memdvect(i) /= d_int(i-(srl_start*C_WIDTH)) THEN
					memdvect(i) := 'X';
			 	END IF;
			 END LOOP;
			 
		   ELSE -- Non SRL16-based
	         FOR i IN offset TO (offset+C_WIDTH-1) LOOP
			 	IF memdvect(i) /= d_int(i-offset) THEN
					memdvect(i) := 'X';
			 	END IF;
   		     END LOOP;
           END IF;
         END IF;
       ELSIF (rat(we_int) = '1') THEN
         IF (anyX(a_int)) THEN
           ASSERT FALSE
             REPORT "Memory Hazard: Writing in a location when address is not defined."
             SEVERITY WARNING;      
           memdvect := (OTHERS => 'X');
         ELSE
           offset := std_logic_vector_2_posint(a_int)*C_WIDTH;
           IF (C_MEM_TYPE = c_srl16) THEN -- Shift the 'X' data into the SRL16s
		     IF (C_ADDR_WIDTH > 4) THEN
		       srl_start := std_logic_vector_2_posint("0000" & a_int_var(4 to c_addr_width-1));	--a_int(C_ADDR_WIDTH-1 downto 4) & "0000");
			 ELSE 
			   srl_start := 0;
			 END IF;
			 srl_end := srl_start + 16;
			 IF srl_end > C_DEPTH THEN
			 	srl_end := C_DEPTH;
			 END IF;
			 
             FOR i IN (srl_end*C_WIDTH)-1 DOWNTO ((srl_start+1)*C_WIDTH) LOOP
				memdvect(i) := memdvect(i-C_WIDTH);
             END LOOP;

			 memdvect(((srl_start+1)*C_WIDTH)-1 DOWNTO (srl_start*C_WIDTH)) := d_int;
			 
		   ELSE -- Non SRL16-based
	         --IF (C_MEM_TYPE = c_dp_ram AND a_int = dpra_int AND rat(we_int) = '1' AND qspo_ce_int = '1') THEN
             --   ASSERT FALSE
             --       REPORT "Memory Hazard: Reading and Writing to same dual port address!"
             --       SEVERITY WARNING;
             --END IF;
             FOR i IN offset TO (offset+C_WIDTH-1) LOOP
	             memdvect(i) := d_int(i-offset);
   		     END LOOP;
           END IF;
         END IF;
       END IF;
     ELSIF (std_logic_vector_2_posint(a_int) >= C_DEPTH) THEN
	 	assert FALSE
			report "Writing to out-of-range address!!"
			severity WARNING;
	 END IF;
   END IF;
	 -- Deal with POSSIBLE rising CLK edge...
	IF(((CLK'event AND 
	   ((rat(CLK) = '1' AND rat(CLK'LAST_VALUE) = 'X') OR
	   (rat(CLK) = 'X' AND rat(CLK'LAST_VALUE) = '0')))) 
		 AND C_MEM_TYPE /= c_rom) THEN

     IF (anyX(a_int) OR std_logic_vector_2_posint(a_int) <  C_DEPTH) THEN
       IF (rat(we_int) = 'X') THEN
         ASSERT FALSE
           REPORT "Memory Hazard: Write enable is not defined at the active clock edge."
           SEVERITY WARNING;      
         IF (anyX(a_int)) THEN
           memdvect := (OTHERS => 'X');
         ELSE
           offset := std_logic_vector_2_posint(a_int)*C_WIDTH;

           IF (C_MEM_TYPE = c_srl16) THEN -- Shift the 'X' data into the SRL16s
		     IF (C_ADDR_WIDTH > 4) THEN
		       srl_start := std_logic_vector_2_posint("0000" & a_int_var(4 to c_addr_width-1));	--a_int(C_ADDR_WIDTH-1 downto 4) & "0000");
			 ELSE 
			   srl_start := 0;
			 END IF;
			 srl_end := srl_start + 16;
			 IF srl_end > C_DEPTH THEN
			 	srl_end := C_DEPTH;
			 END IF;
			 
             FOR i IN (srl_end*C_WIDTH)-1 DOWNTO ((srl_start+1)*C_WIDTH) LOOP
               	IF memdvect(i) /= memdvect(i-C_WIDTH) THEN
			   		memdvect(i) := 'X';
			 	END IF;
             END LOOP;
			 FOR i in ((srl_start+1)*C_WIDTH)-1 DOWNTO (srl_start*C_WIDTH) LOOP
			 	IF memdvect(i) /= d_int(i-(srl_start*C_WIDTH)) THEN
					memdvect(i) := 'X';
			 	END IF;
			 END LOOP;
			 
		   ELSE -- Non SRL16-based
	         --IF (C_MEM_TYPE = c_dp_ram AND a_int = dpra_int AND rat(we_int) = '1' AND qspo_ce_int = '1') THEN
             --   ASSERT FALSE
             --       REPORT "Memory Hazard: Reading and Writing to same dual port address!"
             --       SEVERITY WARNING;
             --END IF;
             FOR i IN offset TO (offset+C_WIDTH-1) LOOP
			 	IF memdvect(i) /= d_int(i-offset) THEN
					memdvect(i) := 'X';
			 	END IF;
   		     END LOOP;
           END IF;

         END IF;
       ELSIF (rat(we_int) = '1') THEN
         IF (anyX(a_int)) THEN
           ASSERT FALSE
             REPORT "Memory Hazard: Writing in a location when address is not defined."
             SEVERITY WARNING;      
           memdvect := (OTHERS => 'X');
         ELSE
           offset := std_logic_vector_2_posint(a_int)*C_WIDTH;

           IF (C_MEM_TYPE = c_srl16) THEN -- Shift the 'X' data into the SRL16s
		     IF (C_ADDR_WIDTH > 4) THEN
		       srl_start := std_logic_vector_2_posint("0000" & a_int_var(4 to c_addr_width-1));	--a_int(C_ADDR_WIDTH-1 downto 4) & "0000");
			 ELSE 
			   srl_start := 0;
			 END IF;
			 srl_end := srl_start + 16;
			 IF srl_end > C_DEPTH THEN
			 	srl_end := C_DEPTH;
			 END IF;
			 
             FOR i IN (srl_end*C_WIDTH)-1 DOWNTO ((srl_start+1)*C_WIDTH) LOOP
               	IF memdvect(i) /= memdvect(i-C_WIDTH) THEN
			   		memdvect(i) := 'X';
			 	END IF;
             END LOOP;
			 FOR i in ((srl_start+1)*C_WIDTH)-1 DOWNTO (srl_start*C_WIDTH) LOOP
			 	IF memdvect(i) /= d_int(i-(srl_start*C_WIDTH)) THEN
					memdvect(i) := 'X';
			 	END IF;
			 END LOOP;
				
		   ELSE -- Non SRL16-based
	         --IF (C_MEM_TYPE = c_dp_ram AND a_int = dpra_int AND rat(we_int) = '1' AND qspo_ce_int = '1') THEN
             --   ASSERT FALSE
             --       REPORT "Memory Hazard: Reading and Writing to same dual port address!"
             --       SEVERITY WARNING;
             --END IF;
             FOR i IN offset TO (offset+C_WIDTH-1) LOOP
			 	IF memdvect(i) /= d_int(i-offset) THEN
					memdvect(i) := 'X';
			 	END IF;
   		     END LOOP;
           END IF;

         END IF;
       END IF;
     ELSIF (std_logic_vector_2_posint(a_int) >= C_DEPTH) THEN
	 	assert FALSE
			report "Writing to out-of-range address!!"
			severity WARNING;
	 END IF;

   END IF;
     -- Bad read enable signal
     IF (rat(re_int) = 'X') THEN
       spo_tmp := (OTHERS => 'X');
       dpo_tmp := (OTHERS => 'X');
	 
	 -- Good read enable signal  
     ELSIF (rat(re_int) = '1') THEN
	 
	   -- Bad address
       IF (anyX(spra_int)) THEN
         spo_tmp := (OTHERS => 'X');
		 
	   -- Good address
       ELSE
         offset := std_logic_vector_2_posint(spra_int);
         IF (offset <  C_DEPTH) THEN
           offset := offset*C_WIDTH;
           FOR i IN 0 TO C_WIDTH-1 LOOP
             spo_tmp(i) := memdvect(offset+i);
           END LOOP;
         ELSIF (C_MUX_TYPE = c_buft_based) THEN
		   assert FALSE
		   		report "Reading from out-of-range address!"
				severity warning;
           spo_tmp := (OTHERS => 'H');
         ELSE
		   assert FALSE
		   		report "Reading from out-of-range address!"
				severity warning;
           spo_tmp := (OTHERS => '0');
         END IF;
       END IF;
	   -- Bad address
       IF (anyX(dpra_int)) THEN
         dpo_tmp := (OTHERS => 'X');

	   -- Good address
       ELSE
         offset := std_logic_vector_2_posint(dpra_int);
         IF (offset <  C_DEPTH) THEN
           offset := offset*C_WIDTH;
           FOR i IN 0 TO C_WIDTH-1 LOOP
             dpo_tmp(i) := memdvect(offset+i);
           END LOOP;
         ELSIF (C_MUX_TYPE = c_buft_based) THEN
		    assert FALSE
	  		report "Reading from out-of-range address!"
			severity warning;
           dpo_tmp := (OTHERS => 'H');
         ELSE
		     assert FALSE
		   		report "Reading from out-of-range address!"
				severity warning;
           dpo_tmp := (OTHERS => '0');
         END IF;
       END IF;
    ELSE
       spo_tmp := (OTHERS => '1');
        dpo_tmp := (OTHERS => '1');
    END IF;

     spo_async < = spo_tmp;
     dpo_async < = dpo_tmp;
 END IF;
   
--
 END PROCESS;
--
END behavioral;


----------------------------------------------------
--  
--  Library Name :  GTS
--  Unit    Name :  lut2
--  Unit    Type :  Text Unit
--  
------------------------------------------------------
--------------------------------------------------------------------------------
--     This file is owned and controlled by Xilinx and must be used           --
--     solely for design, simulation, implementation and creation of          --
--     design files limited to Xilinx devices or technologies. Use            --
--     with non-Xilinx devices or technologies is expressly prohibited        --
--     and immediately terminates your license.                               --
--                                                                            --
--     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"          --
--     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                --
--     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION        --
--     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION            --
--     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS              --
--     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                --
--     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE       --
--     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY               --
--     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                --
--     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR         --
--     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF        --
--     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS        --
--     FOR A PARTICULAR PURPOSE.                                              --
--                                                                            --
--     Xilinx products are not intended for use in life support               --
--     appliances, devices, or systems. Use in such applications are          --
--     expressly prohibited.                                                  --
--                                                                            --
--     (c) Copyright 1995-2004 Xilinx, Inc.                                   --
--     All rights reserved.                                                   --
--------------------------------------------------------------------------------
-- You must compile the wrapper file lut2.vhd when simulating
-- the core, lut2. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Guide".

-- The synopsys directives "translate_off/translate_on" specified
-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).

-- synopsys translate_off
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

Library XilinxCoreLib;
ENTITY lut2 IS
	port (
	A: IN std_logic_VECTOR(3 downto 0);
	SPO: OUT std_logic_VECTOR(47 downto 0));
END lut2;



ARCHITECTURE lut2_a OF lut2 IS

component wrapped_lut2
	port (
	A: IN std_logic_VECTOR(3 downto 0);
	SPO: OUT std_logic_VECTOR(47 downto 0));
end component;

-- Configuration specification 
	for all : wrapped_lut2 use entity XilinxCoreLib.C_DIST_MEM_V7_1(behavioral)
		generic map(
			c_qualify_we => 0,
			c_mem_type => 0,
			c_has_qdpo_rst => 0,
			c_has_qspo => 0,
			c_has_qspo_rst => 0,
			c_has_dpo => 0,
			c_has_qdpo_clk => 0,
			c_has_d => 0,
			c_qce_joined => 0,
			c_width => 48,
			c_reg_a_d_inputs => 0,
			c_latency => 0,
			c_has_we => 0,
			c_has_spo => 1,
			c_depth => 16,
			c_has_i_ce => 0,
			c_default_data => "0",
			c_default_data_radix => 1,
			c_has_dpra => 0,
			c_has_clk => 0,
			c_enable_rlocs => 1,
			c_generate_mif => 1,
			c_has_qspo_ce => 0,
			c_addr_width => 4,
			c_has_qdpo_srst => 0,
			c_mux_type => 0,
			c_has_spra => 0,
			c_has_qdpo => 0,
			c_mem_init_file => "/disk1/users/bellato/GTS/Mezzanine/rom16x48_2/lut2.mif",
			c_reg_dpra_input => 0,
			c_has_rd_en => 0,
			c_has_qspo_srst => 0,
			c_read_mif => 1,
			c_sync_enable => 0,
			c_has_qdpo_ce => 0);
BEGIN

U0 : wrapped_lut2
		port map (
			A => A,
			SPO => SPO);
END lut2_a;

-- synopsys translate_on



----------------------------------------------------
--  
--  Library Name :  GTS
--  Unit    Name :  lut1
--  Unit    Type :  Text Unit
--  
------------------------------------------------------
--------------------------------------------------------------------------------
--     This file is owned and controlled by Xilinx and must be used           --
--     solely for design, simulation, implementation and creation of          --
--     design files limited to Xilinx devices or technologies. Use            --
--     with non-Xilinx devices or technologies is expressly prohibited        --
--     and immediately terminates your license.                               --
--                                                                            --
--     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"          --
--     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                --
--     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION        --
--     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION            --
--     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS              --
--     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                --
--     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE       --
--     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY               --
--     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                --
--     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR         --
--     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF        --
--     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS        --
--     FOR A PARTICULAR PURPOSE.                                              --
--                                                                            --
--     Xilinx products are not intended for use in life support               --
--     appliances, devices, or systems. Use in such applications are          --
--     expressly prohibited.                                                  --
--                                                                            --
--     (c) Copyright 1995-2004 Xilinx, Inc.                                   --
--     All rights reserved.                                                   --
--------------------------------------------------------------------------------
-- You must compile the wrapper file lut1.vhd when simulating
-- the core, lut1. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Guide".

-- The synopsys directives "translate_off/translate_on" specified
-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).

-- synopsys translate_off
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

Library XilinxCoreLib;
ENTITY lut1 IS
	port (
	A: IN std_logic_VECTOR(3 downto 0);
	SPO: OUT std_logic_VECTOR(47 downto 0));
END lut1;



ARCHITECTURE lut1_a OF lut1 IS

component wrapped_lut1
	port (
	A: IN std_logic_VECTOR(3 downto 0);
	SPO: OUT std_logic_VECTOR(47 downto 0));
end component;

-- Configuration specification 
	for all : wrapped_lut1 use entity XilinxCoreLib.C_DIST_MEM_V7_1(behavioral)
		generic map(
			c_qualify_we => 0,
			c_mem_type => 0,
			c_has_qdpo_rst => 0,
			c_has_qspo => 0,
			c_has_qspo_rst => 0,
			c_has_dpo => 0,
			c_has_qdpo_clk => 0,
			c_has_d => 0,
			c_qce_joined => 0,
			c_width => 48,
			c_reg_a_d_inputs => 0,
			c_latency => 0,
			c_has_we => 0,
			c_has_spo => 1,
			c_depth => 16,
			c_has_i_ce => 0,
			c_default_data => "0",
			c_default_data_radix => 1,
			c_has_dpra => 0,
			c_has_clk => 0,
			c_enable_rlocs => 1,
			c_generate_mif => 1,
			c_has_qspo_ce => 0,
			c_addr_width => 4,
			c_has_qdpo_srst => 0,
			c_mux_type => 0,
			c_has_spra => 0,
			c_has_qdpo => 0,
			c_mem_init_file => "/disk1/users/bellato/GTS/Mezzanine/rom16x48_1/lut1.mif",
			c_reg_dpra_input => 0,
			c_has_rd_en => 0,
			c_has_qspo_srst => 0,
			c_read_mif => 1,
			c_sync_enable => 0,
			c_has_qdpo_ce => 0);
BEGIN

U0 : wrapped_lut1
		port map (
			A => A,
			SPO => SPO);
END lut1_a;

-- synopsys translate_on



----------------------------------------------------
--  
--  Library Name :  GTS
--  Unit    Name :  t_decode
--  Unit    Type :  Text Unit
--  
------------------------------------------------------
------------------------------------------
------------------------------------------
-- Date        : Sun Mar 20 21:13:01 2005
--
-- Author      : 
--
-- Company     : 
--
-- Description : 
--
------------------------------------------
------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;


entity  t_decode  is
port (bclk, lreset : in std_logic;
      tstamp_err : out std_logic;
      fiber_in : in std_logic_vector (15 downto 0);
      msk1 : in std_logic_vector (47 downto 0);
      msk2 : in std_logic_vector (47 downto 0);
      timestamp : out std_logic_vector (47 downto 0);
      timestamp_lsw : out std_logic_vector (15 downto 0)
);
end;


------------------------------------------
------------------------------------------
-- Date        : Sun Mar 20 21:13:01 2005
--
-- Author      : 
--
-- Company     : 
--
-- Description : 
--
------------------------------------------
------------------------------------------
architecture  t_dec  of  t_decode  is

signal current, previous : std_logic_vector(47 downto 0);
begin

  process (bclk,lreset)
  
  variable evNumL,tmp : unsigned (47 downto 0);
  variable nib1,nib2 : std_logic_vector(3 downto 0);
   begin
     if lreset ='1' then
          current < = (others=>'0');
          previous < = (others=>'0');
     elsif (bclk'event and bclk='1') then
          evNumL := unsigned(current);
          nib1 := fiber_in(3 downto 0);
          nib2 := fiber_in(7 downto 4);
          if nib2(3)='1'  then
             evNumL := evNumL and unsigned(msk1);
             tmp := unsigned ("00000000000000000000000000000000000000000000" & (nib2 and "0111"));
             tmp := SHIFT_LEFT(tmp,to_integer(1+3*(unsigned(nib1))));
             evNumL := evNumL or tmp;
          else
             evNumL(3 downto 0) := unsigned(nib1);
             evNumL := evNumL and unsigned(msk2);
             tmp := unsigned ("00000000000000000000000000000000000000000000" & (nib2 and "0111"));
             tmp := SHIFT_LEFT(tmp,to_integer(1+3*(unsigned(nib1))));
             evNumL :=evNumL or tmp;
          end if;
          if evNumL /= (unsigned(previous)+1) then
            tstamp_err < ='1';
          else
            tstamp_err < ='0';
          end if;
          previous < = current;
          current < = std_logic_vector(evNumL);
          timestamp < = std_logic_vector(evNumL);
          timestamp_lsw < = std_logic_vector(evNumL(15 downto 0));
      end if;
    end process;
end t_dec;

----------------------------------------------------
--  
--  Library Name :  GTS
--  Unit    Name :  RTX
--  Unit    Type :  Block Diagram
--  
------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
 
 
entity RTX is
  port (
        timestamp_lsw : out std_logic_vector(15 downto 0 );
        tstamp_err : out std_logic;
        L1A : out std_logic_vector(15 downto 0 );
        lreset : in std_logic;
        timestamp : out std_logic_vector(47 downto 0 );
        RXBUFSTATUS : out std_logic_vector(1 downto 0 );
        refclksel : in std_logic;
        bcast_out : out std_logic_vector(7 downto 0 );
        fiber_in_n : in std_logic;
        fiber_in_p : in std_logic;
        RXREALIGN : out std_logic;
        fiber_out_n : out std_logic;
        l_tag : in std_logic_vector(7 downto 0 );
        TXKERR : out std_logic_vector(1 downto 0 );
        fiber_out_p : out std_logic;
        gclk : out std_logic;
        CONFIGOUT : out std_logic;
        CHBONDDONE : out std_logic;
        L1A_fifo_full : in std_logic;
        event_num : out std_logic_vector(23 downto 0 );
        L1A_fifo_wr_en : out std_logic;
        msg_in : in std_logic_vector(7 downto 0 );
        RXCOMMADET : out std_logic;
        RXCHARISK : out std_logic_vector(1 downto 0 );
        msg_strobe : in std_logic_vector(1 downto 0 );
        RXNOTINTABLE : out std_logic_vector(1 downto 0 );
        bcast_strobe : out std_logic;
        RXRUNDISP : out std_logic_vector(1 downto 0 );
        TXBUFERR : out std_logic;
        RXDISPERR : out std_logic_vector(1 downto 0 );
        TXRUNDISP : out std_logic_vector(1 downto 0 );
        RXCLKCORCNT : out std_logic_vector(2 downto 0 );
        backpressure : in std_logic;
        gts_clk : out std_logic;
        l_trg : in std_logic_vector(1 downto 0 );
        RXCHARISCOMMA : out std_logic_vector(1 downto 0 );
        RXCHECKINGCRC : out std_logic;
        RXCRCERR : out std_logic;
        reset : out std_logic;
        lclk : in std_logic
        );
 
 
end RTX;
 
 
use work.all;
architecture RTX of RTX is
 
  signal g : std_logic;
  signal L1A_arrived : std_logic;
  signal TXDATA : std_logic_vector(15 downto 0 );
  signal TXBYPASS8B10B : std_logic_vector(1 downto 0 );
  signal msb : std_logic_vector(7 downto 0 );
  signal msk1 : std_logic_vector(47 downto 0 );
  signal msk2 : std_logic_vector(47 downto 0 );
  signal outofsync : std_logic;
  signal rxdata : std_logic_vector(15 downto 0 );
  signal S35 : std_logic;
  signal O : std_logic;
  signal S36 : std_logic;
  signal bclk : std_logic;
  signal I1 : std_logic;
  signal EQ : std_logic;
  signal S90 : std_logic;
  signal I2 : std_logic;
  signal S26 : std_logic;
  signal S24 : std_logic;
  signal S78 : std_logic_vector(15 downto 0 );
  signal nibble2 : std_logic_vector(3 downto 0 );
  signal S44 : std_logic;
  signal nibble1 : std_logic_vector(3 downto 0 );
  signal RXRECCLK : std_logic;
  signal TXCHARISK : std_logic_vector(1 downto 0 );
  signal LOOPBACK : std_logic_vector(1 downto 0 );
  signal RXLOSSOFSYNC : std_logic_vector(1 downto 0 );
  component t_decode
      port (
            bclk : in std_logic;
            lreset : in std_logic;
            tstamp_err : out std_logic;
            fiber_in : in std_logic_vector(15 downto 0 );
            msk1 : in std_logic_vector(47 downto 0 );
            msk2 : in std_logic_vector(47 downto 0 );
            timestamp : out std_logic_vector(47 downto 0 );
            timestamp_lsw : out std_logic_vector(15 downto 0 )
            );
  end component;
  component lut1
      port (
            A : in std_logic_vector(3 downto 0 );
            SPO : out std_logic_vector(47 downto 0 )
            );
  end component;
  component lut2
      port (
            A : in std_logic_vector(3 downto 0 );
            SPO : out std_logic_vector(47 downto 0 )
            );
  end component;
  component cmd_dec
      port (
            bcast_out : out std_logic_vector(7 downto 0 );
            DoubleErr : out std_ulogic;
            event_num : out std_logic_vector(23 downto 0 );
            MultipleErr : out std_ulogic;
            SingleErr : out std_ulogic;
            outofsync : in std_logic;
            bclk : in std_logic;
            L1A : out std_logic_vector(15 downto 0 );
            msb : in std_logic_vector(7 downto 0 );
            L1A_arrived : out std_logic;
            lreset : in std_logic;
            bcast_strobe : out std_logic;
            CheckOut : out std_logic_vector(0 to 3 );
            reset : out std_logic
            );
  end component;
  component MGT_custom
      port (
            CONFIGENABLE : in std_logic;
            CONFIGIN : in std_logic;
            ENMCOMMAALIGN : in std_logic;
            ENPCOMMAALIGN : in std_logic;
            ENCHANSYNC : in std_logic;
            LOOPBACK : in std_logic_vector(1 downto 0 );
            POWERDOWN : in std_logic;
            REFCLK : in std_logic;
            REFCLK2 : in std_logic;
            REFCLKSEL : in std_logic;
            BREFCLK : in std_logic;
            BREFCLK2 : in std_logic;
            RXN : in std_logic;
            RXP : in std_logic;
            RXPOLARITY : in std_logic;
            RXRESET : in std_logic;
            RXUSRCLK : in std_logic;
            RXUSRCLK2 : in std_logic;
            TXBYPASS8B10B : in std_logic_vector(1 downto 0 );
            TXCHARDISPMODE : in std_logic_vector(1 downto 0 );
            TXCHARDISPVAL : in std_logic_vector(1 downto 0 );
            TXCHARISK : in std_logic_vector(1 downto 0 );
            TXDATA : in std_logic_vector(15 downto 0 );
            TXFORCECRCERR : in std_logic;
            TXINHIBIT : in std_logic;
            TXPOLARITY : in std_logic;
            TXRESET : in std_logic;
            TXUSRCLK : in std_logic;
            TXUSRCLK2 : in std_logic;
            CHBONDDONE : out std_logic;
            CONFIGOUT : out std_logic;
            RXBUFSTATUS : out std_logic_vector(1 downto 0 );
            RXCHARISCOMMA : out std_logic_vector(1 downto 0 );
            RXCHARISK : out std_logic_vector(1 downto 0 );
            RXCHECKINGCRC : out std_logic;
            RXCLKCORCNT : out std_logic_vector(2 downto 0 );
            RXCOMMADET : out std_logic;
            RXCRCERR : out std_logic;
            RXDATA : out std_logic_vector(15 downto 0 );
            RXDISPERR : out std_logic_vector(1 downto 0 );
            RXLOSSOFSYNC : out std_logic_vector(1 downto 0 );
            RXNOTINTABLE : out std_logic_vector(1 downto 0 );
            RXREALIGN : out std_logic;
            RXRECCLK : out std_logic;
            RXRUNDISP : out std_logic_vector(1 downto 0 );
            TXBUFERR : out std_logic;
            TXKERR : out std_logic_vector(1 downto 0 );
            TXN : out std_logic;
            TXP : out std_logic;
            TXRUNDISP : out std_logic_vector(1 downto 0 )
            );
  end component;
  component cmd_enc
      port (
            DoubleErr : out std_ulogic;
            l_tag : in std_logic_vector(7 downto 0 );
            TXDATA : out std_logic_vector(15 downto 0 );
            MultipleErr : out std_ulogic;
            msg_in : in std_logic_vector(7 downto 0 );
            SingleErr : out std_ulogic;
            bclk : in std_logic;
            msg_strobe : in std_logic_vector(1 downto 0 );
            lreset : in std_logic;
            backpressure : in std_logic;
            l_trg : in std_logic_vector(1 downto 0 );
            DataCorr : out std_logic_vector(0 to 7 )
            );
  end component;
  component L1A_fifo_ctrl
      port (
            bclk : in std_logic;
            lreset : in std_logic;
            L1A_fifo_wr_en : out std_logic;
            L1A_fifo_full : in std_logic;
            L1A_arrived : in std_logic
            );
  end component;
 
  -- Start Configuration Specification
  -- ++ for all : t_decode use entity work.t_decode(t_dec);
  -- ++ for all : lut1 use entity work.lut1(lut1_a);
  -- ++ for all : lut2 use entity work.lut2(lut2_a);
  -- ++ for all : cmd_dec use entity work.cmd_dec(cmd_dec);
  -- ++ for all : MGT_custom use entity work.MGT_custom(STRUCT);
  -- ++ for all : cmd_enc use entity work.cmd_enc(cmd_enc);
  -- ++ for all : L1A_fifo_ctrl use entity work.L1A_fifo_ctrl(L1A_fifo_ctrl);
  -- End Configuration Specification
 
begin
 
  inst_t_decode: t_decode
    port map (
              bclk => bclk,
              lreset => lreset,
              tstamp_err => tstamp_err,
              fiber_in => rxdata(15 downto 0),
              msk1 => msk1(47 downto 0),
              msk2 => msk2(47 downto 0),
              timestamp => timestamp(47 downto 0),
              timestamp_lsw => timestamp_lsw(15 downto 0)
              );
 
  C8: lut1
    port map (
              A => nibble1(3 downto 0),
              SPO => msk1(47 downto 0)
              );
 
  C9: lut2
    port map (
              A => nibble2(3 downto 0),
              SPO => msk2(47 downto 0)
              );
 
  inst_cmd_dec: cmd_dec
    port map (
              bcast_out => bcast_out(7 downto 0),
              DoubleErr => open,
              event_num => event_num(23 downto 0),
              MultipleErr => open,
              SingleErr => open,
              outofsync => outofsync,
              bclk => bclk,
              L1A => L1A(15 downto 0),
              msb => msb(7 downto 0),
              L1A_arrived => L1A_arrived,
              lreset => lreset,
              bcast_strobe => bcast_strobe,
              CheckOut => open,
              reset => reset
              );
 
  C12: MGT_custom
    port map (
              CONFIGENABLE => O,
              CONFIGIN => O,
              ENMCOMMAALIGN => S24,
              ENPCOMMAALIGN => S24,
              ENCHANSYNC => S26,
              LOOPBACK => LOOPBACK(1 downto 0),
              POWERDOWN => S26,
              REFCLK => lclk,
              REFCLK2 => bclk,
              REFCLKSEL => refclksel,
              BREFCLK => g,
              BREFCLK2 => g,
              RXN => fiber_in_n,
              RXP => fiber_in_p,
              RXPOLARITY => S35,
              RXRESET => lreset,
              RXUSRCLK => bclk,
              RXUSRCLK2 => bclk,
              TXBYPASS8B10B => TXBYPASS8B10B(1 downto 0),
              TXCHARDISPMODE => TXBYPASS8B10B(1 downto 0),
              TXCHARDISPVAL => TXBYPASS8B10B(1 downto 0),
              TXCHARISK => TXCHARISK(1 downto 0),
              TXDATA => TXDATA(15 downto 0),
              TXFORCECRCERR => S44,
              TXINHIBIT => S44,
              TXPOLARITY => S44,
              TXRESET => lreset,
              TXUSRCLK => bclk,
              TXUSRCLK2 => bclk,
              CHBONDDONE => CHBONDDONE,
              CONFIGOUT => CONFIGOUT,
              RXBUFSTATUS => RXBUFSTATUS(1 downto 0),
              RXCHARISCOMMA => RXCHARISCOMMA(1 downto 0),
              RXCHARISK => RXCHARISK(1 downto 0),
              RXCHECKINGCRC => RXCHECKINGCRC,
              RXCLKCORCNT => RXCLKCORCNT(2 downto 0),
              RXCOMMADET => RXCOMMADET,
              RXCRCERR => RXCRCERR,
              RXDATA => rxdata(15 downto 0),
              RXDISPERR => RXDISPERR(1 downto 0),
              RXLOSSOFSYNC => RXLOSSOFSYNC(1 downto 0),
              RXNOTINTABLE => RXNOTINTABLE(1 downto 0),
              RXREALIGN => RXREALIGN,
              RXRECCLK => RXRECCLK,
              RXRUNDISP => RXRUNDISP(1 downto 0),
              TXBUFERR => TXBUFERR,
              TXKERR => TXKERR(1 downto 0),
              TXN => fiber_out_n,
              TXP => fiber_out_p,
              TXRUNDISP => TXRUNDISP(1 downto 0)
              );
 
  inst_cmd_enc: cmd_enc
    port map (
              DoubleErr => open,
              l_tag => l_tag(7 downto 0),
              TXDATA => TXDATA(15 downto 0),
              MultipleErr => open,
              msg_in => msg_in(7 downto 0),
              SingleErr => open,
              bclk => bclk,
              msg_strobe => msg_strobe(1 downto 0),
              lreset => lreset,
              backpressure => backpressure,
              l_trg => l_trg(1 downto 0),
              DataCorr => open
              );
 
  inst_L1A_fifo_ctrl: L1A_fifo_ctrl
    port map (
              bclk => bclk,
              lreset => lreset,
              L1A_fifo_wr_en => L1A_fifo_wr_en,
              L1A_fifo_full => L1A_fifo_full,
              L1A_arrived => L1A_arrived
              );
 
  nibble2(3 downto 0) < = rxdata(3 downto 0);
  msb(7 downto 0) < = rxdata(15 downto 8);
  nibble1(3 downto 0) < = rxdata(3 downto 0);
 
  gclk < = RXRECCLK;
  gts_clk < = RXRECCLK;
  bclk < = RXRECCLK;
 
      O < = '0';
 
      S24 < = '1';
 
      S26 < = '0';
 
  LOOPBACK(1) < = S26;
  LOOPBACK(0) < = S26;
 
      g < = '0';
 
      S35 < = '0';
 
      S36 < = '0';
 
  TXBYPASS8B10B(1) < = S36;
  TXBYPASS8B10B(0) < = S36;
 
      S44 < = '0';
 
 
  process (TXDATA , S78)
   begin
      if ((TXDATA(15 downto 0)) = (S78(15 downto 0))) then
        EQ < = '1';
      else
        EQ < = '0';
      end if;
  end process;
 
 
  S78(15 downto 0) < = "0011110000000000";
 
 
  TXCHARISK(1) < = EQ;
  TXCHARISK(0) < = S90;
 
      S90 < = '0';
 
   outofsync < = ( I1) or ( I2);
 
 
  I1 < = RXLOSSOFSYNC(1);
  I2 < = RXLOSSOFSYNC(0);
end RTX;