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--     design files limited to Xilinx devices or technologies. Use            --
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-- You must compile the wrapper file lut_b.vhd when simulating
-- the core, lut_b. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".

-- The synopsys directives "translate_off/translate_on" specified
-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synopsys translate_off
Library XilinxCoreLib;
-- synopsys translate_on
ENTITY lut_b IS
	port (
	A: IN std_logic_VECTOR(3 downto 0);
	SPO: OUT std_logic_VECTOR(47 downto 0));
END lut_b;