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--  
--      VHDL code generated by Visual Elite
--
--  Design Unit:
--  ------------
--      Unit    Name  :  T_valreject_ctrl
--      Library Name  :  GTS_IF
--  
--      Creation Date :  Sun Mar 27 14:40:15 2005
--      Version       :  3.7.1 build 3. Date: Dec 27 2004. License: 2004.12
--  
--  Options Used:
--  -------------
--      Target
--         Language   :  As Is
--         Purpose    :  Synthesis
--         Vendor     :  Design Compiler
--  
--      Style
--         Use Procedures                 :  No
--         Code Destination               :  Combined file
--         Attach Packages                :  No
--         Generate Entity                :  Yes
--         Attach Directives              :  Yes
--         Structural                     :  No
--         Configuration Specification    :  No
--         library name in
--         Configuration Specification    :  No
--         Configuration Declaration      :  None
--         IF for state selection         :  No
--         Preserve spacing for free text :  Yes
--         Declaration alignment          :  No
--
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----------------------------------------------------
--  
--  Library Name :  GTS_IF
--  Unit    Name :  T_valreject_ctrl
--  Unit    Type :  State Machine
--  
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library ieee;
use ieee.std_logic_1164.all;
library SYNOPSYS;
use SYNOPSYS.ATTRIBUTES.ALL;
 
 
entity T_valreject_ctrl is
  port (
        gclk : in std_logic;
        reset : in std_logic;
        trigger_validation : out std_logic;
        trigger_rejection : out std_logic;
        val_reject_bus : out std_logic_vector(7 downto 0 );
        validate : in std_logic;
        rejecta : in std_logic;
        validate_ack : out std_logic;
        reject_ack : out std_logic;
        vaLreject_tag : in std_logic_vector(47 downto 0 )
        );
 
end T_valreject_ctrl;
 
 
architecture T_valreject_ctrl of T_valreject_ctrl is
 
  type visual_S0_states is (S0, S1, S10, S11, S12, S2, S3, S4, S5, S6, S7, S8,
                            S9);
 
  signal visual_S0_current : visual_S0_states;
  attribute STATE_VECTOR of T_valreject_ctrl :
            architecture is "visual_S0_current";
 
 
begin
 
 
 
  -- Synchronous process
  T_valreject_ctrl_S0:
  process (gclk, reset)
  begin
 
    if (reset = '0') then
      trigger_validation < = 'X';
      validate_ack < = 'X';
      reject_ack < = 'X';
      val_reject_bus < = (others => 'X');
      trigger_rejection < = 'X';
      visual_S0_current < = S0;
    elsif (gclk'event and gclk = '1') then
 
      case visual_S0_current is
        when S0 =>
          if (rejecta = '1') then
            trigger_rejection< ='1';
            val_reject_bus< =valreject_tag(47 downto 40);
            visual_S0_current < = S1;
          elsif (validate = '1') then
            trigger_validation< ='1';
            val_reject_bus< =valreject_tag(47 downto 40);
            visual_S0_current < = S6;
          else
            visual_S0_current < = S0;
          end if;
 
        when S1 =>
          trigger_rejection< ='0';
          val_reject_bus< =valreject_tag(39 downto 32);
          visual_S0_current < = S2;
 
        when S10 =>
          val_reject_bus< =valreject_tag(7 downto 0);
          validate_ack< ='1';
          visual_S0_current < = S12;
 
        when S11 =>
          if (rejecta = '0') then
            visual_S0_current < = S0;
          else
            visual_S0_current < = S11;
          end if;
 
        when S12 =>
          if (validate = '0') then
            visual_S0_current < = S0;
          else
            visual_S0_current < = S12;
          end if;
 
        when S2 =>
          val_reject_bus< =valreject_tag(31 downto 24);
          visual_S0_current < = S3;
 
        when S3 =>
          val_reject_bus< =valreject_tag(23 downto 16);
          visual_S0_current < = S4;
 
        when S4 =>
          val_reject_bus< =valreject_tag(15 downto 8);
          visual_S0_current < = S5;
 
        when S5 =>
          val_reject_bus< =valreject_tag(7 downto 0);
          reject_ack< ='1';
          visual_S0_current < = S11;
 
        when S6 =>
          trigger_validation< ='0';
          val_reject_bus< =valreject_tag(39 downto 32);
          visual_S0_current < = S7;
 
        when S7 =>
          val_reject_bus< =valreject_tag(31 downto 24);
          visual_S0_current < = S8;
 
        when S8 =>
          val_reject_bus< =valreject_tag(23 downto 16);
          visual_S0_current < = S9;
 
        when S9 =>
          val_reject_bus< =valreject_tag(15 downto 8);
          visual_S0_current < = S10;
 
        when others =>
 
          visual_S0_current < = S0;
      end case;
    end if;
  end process T_valreject_ctrl_S0;
 
end T_valreject_ctrl;