----------------------------------------------------
--  
--      VHDL code generated by Visual Elite
--
--  Design Unit:
--  ------------
--      Unit    Name  :  trigger_match
--      Library Name  :  GTS_IF
--  
--      Creation Date :  Sun Mar 27 14:39:57 2005
--      Version       :  3.7.1 build 3. Date: Dec 27 2004. License: 2004.12
--  
--  Options Used:
--  -------------
--      Target
--         Language   :  As Is
--         Purpose    :  Synthesis
--         Vendor     :  Design Compiler
--  
--      Style
--         Use Procedures                 :  No
--         Code Destination               :  Combined file
--         Attach Packages                :  No
--         Generate Entity                :  Yes
--         Attach Directives              :  Yes
--         Structural                     :  No
--         Configuration Specification    :  No
--         library name in
--         Configuration Specification    :  No
--         Configuration Declaration      :  None
--         IF for state selection         :  No
--         Preserve spacing for free text :  Yes
--         Declaration alignment          :  No
--
----------------------------------------------------
----------------------------------------------------
--  
--  Library Name :  GTS_IF
--  Unit    Name :  trigger_match
--  Unit    Type :  State Machine
--  
------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.NUMERIC_STD.all;
library SYNOPSYS;
use SYNOPSYS.ATTRIBUTES.ALL;
 
 
entity trigger_match is
  port (
        L1A_fifo_rd_en : out std_logic;
        gclk : in std_logic;
        reset : in std_logic;
        L1A_fifo_empty : in std_logic;
        T_request_fifo_rd_en : out std_logic;
        L1A_fifo_dout : in std_logic_vector(15 downto 0 );
        L1A_fifo_rd_data_count : in std_logic_vector(5 downto 0 );
        L1A_fifo_wr_data_count : in std_logic_vector(5 downto 0 );
        T_request_fifo_empty : in std_logic;
        T_request_fifo_dout : in std_logic_vector(47 downto 0 );
        T_request_fifo_rd_data_empty : in std_logic_vector(5 downto 0 );
        validate : out std_logic;
        rejecta : out std_logic;
        validate_ack : in std_logic;
        reject_ack : in std_logic;
        L1A_latency : in std_logic_vector(15 downto 0 );
        matching_window : in std_logic_vector(15 downto 0 );
        timestamp_lsw : in std_logic_vector(15 downto 0 );
        vaLreject_tag : out std_logic_vector(47 downto 0 )
        );
 
end trigger_match;
 
 
architecture trigger_match of trigger_match is
 
  constant REJECT_TIME : unsigned(16 downto 0 ) := "00000010000000000";  --  400
  constant MOD_MASK : unsigned(16 downto 0 ) := "10000000000000000";  --  1**16
  signal match_high : unsigned(16 downto 0 );
  signal match_low : unsigned(16 downto 0 );
  signal event_time : unsigned(16 downto 0 );
  signal L1A_time : unsigned(16 downto 0 );
  signal trigger_matched : std_logic;
  signal ev_discard : std_logic;
  signal max_elapsed : unsigned(16 downto 0 );
  signal elapsed : unsigned(16 downto 0 );
 
  type visual_RST_S_states is (RST_S, M1, M2, M3, M4, M5, M6, M7, R1, R2, R3, R4
                               , R5, check_l1a_fifo, match_start, reject_start,
                               S0, S1, S10, S2, S3, S4, S5, S6, S7, S8, S9);
 
  signal visual_RST_S_current : visual_RST_S_states;
  attribute STATE_VECTOR of trigger_match :
            architecture is "visual_RST_S_current";
 
 
begin
 
 
 
  -- Synchronous process
  trigger_match_RST_S:
  process (gclk, reset)
  begin
 
    if (reset = '0') then
      rejecta < = 'X';
      max_elapsed < = (others => 'X');
      validate < = 'X';
      vaLreject_tag < = (others => 'X');
      T_request_fifo_rd_en < = 'X';
      match_high < = (others => 'X');
      match_low < = (others => 'X');
      elapsed < = (others => 'X');
      event_time < = (others => 'X');
      L1A_time < = (others => 'X');
      L1A_fifo_rd_en < = 'X';
      trigger_matched< ='0';
      ev_discard< ='0';
      visual_RST_S_current < = RST_S;
    elsif (gclk'event and gclk = '1') then
 
      case visual_RST_S_current is
        when RST_S =>
          visual_RST_S_current < = check_l1a_fifo;
 
        when M1 =>
          if (T_request_fifo_empty = '0') then
            event_time< =unsigned('0' & T_request_fifo_dout(15 downto 0));
            visual_RST_S_current < = M2;
          else
            visual_RST_S_current < = check_l1a_fifo;
          end if;
 
        when M2 =>
          elapsed < =(unsigned('0' & timestamp_lsw) - event_time)  mod MOD_MASK;
          match_low< =(L1A_time - unsigned('0' & L1A_latency)) mod MOD_MASK;
          visual_RST_S_current < = M3;
 
        when M3 =>
          match_high< =(match_low + unsigned('0'& matching_window)) mod MOD_MASK;
          visual_RST_S_current < = M4;
 
        when M4 =>
          visual_RST_S_current < = S0;
 
        when M5 =>
          if (trigger_matched = '1') then
            vaLreject_tag< =T_request_fifo_dout;
            validate< ='1';
            T_request_fifo_rd_en< ='0';
            visual_RST_S_current < = M6;
          elsif (ev_discard = '1') then
            vaLreject_tag< =T_request_fifo_dout;
            rejecta< ='1';
            T_request_fifo_rd_en< ='0';
            visual_RST_S_current < = R4;
          else
            visual_RST_S_current < = check_l1a_fifo;
          end if;
 
        when M6 =>
          if (validate_ack = '1') then
            validate< ='0';
            visual_RST_S_current < = M7;
          else
            visual_RST_S_current < = M6;
          end if;
 
        when M7 =>
          visual_RST_S_current < = check_l1a_fifo;
 
        when R1 =>
          max_elapsed < =(unsigned('0' & timestamp_lsw) - event_time) mod MOD_MASK;
          visual_RST_S_current < = R2;
 
        when R2 =>
          if (max_elapsed >= REJECT_TIME) then
            T_request_fifo_rd_en< ='1';
            visual_RST_S_current < = R3;
          else
            visual_RST_S_current < = check_l1a_fifo;
          end if;
 
        when R3 =>
          vaLreject_tag< =T_request_fifo_dout;
          rejecta< ='1';
          T_request_fifo_rd_en< ='0';
          visual_RST_S_current < = R4;
 
        when R4 =>
          if (reject_ack = '1') then
            rejecta< ='0';
            visual_RST_S_current < = R5;
          else
            visual_RST_S_current < = R4;
          end if;
 
        when R5 =>
          visual_RST_S_current < = check_l1a_fifo;
 
        when check_l1a_fifo =>
          if (L1A_fifo_empty = '0') then
            L1A_fifo_rd_en< ='1';
            visual_RST_S_current < = match_start;
          else
            visual_RST_S_current < = reject_start;
          end if;
 
        when match_start =>
          L1A_fifo_rd_en< ='0';
          L1A_time< =unsigned('0' & L1A_fifo_dout);
          trigger_matched< ='0';
          ev_discard< ='0';
          visual_RST_S_current < = M1;
 
        when reject_start =>
          if (T_request_fifo_empty = '0') then
            event_time< =unsigned('0' & T_request_fifo_dout(15 downto 0));
            visual_RST_S_current < = R1;
          else
            visual_RST_S_current < = check_l1a_fifo;
          end if;
 
        when S0 =>
          if (match_high > match_low) then
            visual_RST_S_current < = S1;
          else
            visual_RST_S_current < = S4;
          end if;
 
        when S1 =>
          if (event_time > match_low and event_time < = match_high) then
            trigger_matched < = '1';
            ev_discard < = '0';
            visual_RST_S_current < = S2;
          else
            visual_RST_S_current < = S6;
          end if;
 
        when S10 =>
          T_request_fifo_rd_en< ='1';
          visual_RST_S_current < = M5;
 
        when S2 =>
          T_request_fifo_rd_en< ='1';
          visual_RST_S_current < = M5;
 
        when S3 =>
          T_request_fifo_rd_en< ='1';
          visual_RST_S_current < = M5;
 
        when S4 =>
          if (((event_time > match_low) and (event_time < = MOD_MASK)) or ((
              event_time >= 0) and (event_time < = match_high))) then
            trigger_matched < = '1';
            ev_discard < = '0';
            visual_RST_S_current < = S8;
          else
            visual_RST_S_current < = S5;
          end if;
 
        when S5 =>
          if ((event_time - match_high) < = (match_low - event_time)) then
            trigger_matched < = '0';
            ev_discard < = '0';
            visual_RST_S_current < = S9;
          else
            trigger_matched < = '0';
            ev_discard < = '1';
            visual_RST_S_current < = S10;
          end if;
 
        when S6 =>
          if (event_time < = match_low) then
            trigger_matched < = '0';
            ev_discard < = '1';
            visual_RST_S_current < = S3;
          else
            trigger_matched < = '0';
            ev_discard < = '0';
            visual_RST_S_current < = S7;
          end if;
 
        when S7 =>
          T_request_fifo_rd_en< ='1';
          visual_RST_S_current < = M5;
 
        when S8 =>
          T_request_fifo_rd_en< ='1';
          visual_RST_S_current < = M5;
 
        when S9 =>
          T_request_fifo_rd_en< ='1';
          visual_RST_S_current < = M5;
 
        when others =>
 
          trigger_matched< ='0';
          ev_discard< ='0';
          visual_RST_S_current < = RST_S;
      end case;
    end if;
  end process trigger_match_RST_S;
 
end trigger_match;