----------------------------------------------------
--  
--      VHDL code generated by Visual Elite
--
--  Design Unit:
--  ------------
--      Unit    Name  :  trigger_match
--      Library Name  :  GTS_IF
--  
--      Creation Date :  Sun Mar 20 08:44:45 2005
--      Version       :  3.7.1 build 3. Date: Dec 27 2004. License: 2004.12
--  
--  Options Used:
--  -------------
--      Target
--         Language   :  As Is
--         Purpose    :  Synthesis
--         Vendor     :  Design Compiler
--  
--      Style
--         Use Procedures                 :  No
--         Code Destination               :  Combined file
--         Attach Packages                :  No
--         Generate Entity                :  Yes
--         Attach Directives              :  Yes
--         Structural                     :  No
--         Configuration Specification    :  No
--         library name in
--         Configuration Specification    :  No
--         Configuration Declaration      :  None
--         IF for state selection         :  No
--         Preserve spacing for free text :  Yes
--         Declaration alignment          :  No
--
----------------------------------------------------
----------------------------------------------------
--  
--  Library Name :  GTS_IF
--  Unit    Name :  trigger_match
--  Unit    Type :  State Machine
--  
------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.NUMERIC_STD.all;
entity stim0 is
  port (
        L1A_fifo_rd_en : in std_logic;
        gclk : inout std_logic;
        reset : inout std_logic;
        L1A_fifo_empty : inout std_logic;
        T_request_fifo_rd_en : in std_logic;
        L1A_fifo_dout : inout std_logic_vector(15 downto 0 );
        L1A_fifo_rd_data_count : inout std_logic_vector(5 downto 0 );
        L1A_fifo_wr_data_count : inout std_logic_vector(5 downto 0 );
        T_request_fifo_empty : inout std_logic;
        T_request_fifo_dout : inout std_logic_vector(47 downto 0 );
        T_request_fifo_rd_data_empty : inout std_logic_vector(5 downto 0 );
        validate : in std_logic;
        rejecta : in std_logic;
        validate_ack : inout std_logic;
        reject_ack : inout std_logic;
        L1A_latency : inout std_logic_vector(15 downto 0 );
        matching_window : inout std_logic_vector(15 downto 0 );
        timestamp_lsw : inout std_logic_vector(15 downto 0 );
        vaLreject_tag : in std_logic_vector(47 downto 0 )
        );
 
 
end stim0;
 
-- entity trigger_match is
-- port (
--   L1A_fifo_rd_en : in std_logic;
--   reset : inout std_logic;
--   L1A_fifo_empty : inout std_logic;
--   T_request_fifo_rd_en : in std_logic;
--   L1A_fifo_dout : inout std_logic_vector;
--   L1A_fifo_rd_data_count : inout std_logic_vector;
--   L1A_fifo_wr_data_count : inout std_logic_vector;
--   T_request_fifo_empty : inout std_logic;
--   T_request_fifo_dout : inout std_logic_vector;
--   T_request_fifo_rd_data_empty : inout std_logic_vector;
--   validate : in std_logic;
--   rejecta : in std_logic;
--   validate_ack : inout std_logic;
--   reject_ack : inout std_logic;
--   L1A_latency : inout std_logic_vector;
--   matching_window : inout std_logic_vector;
--   timestamp_lsw : inout std_logic_vector;
--   vaLreject_tag : in std_logic_vector;
--   gclk : inout std_logic
-- );
-- end trigger_match;
 
 
architecture trigger_match of stim0 is
 
begin
  process
  begin
    reset < = '0';
    wait  for 61 ns;
    reset < = '1';
    wait  for 9939 ns;
    wait ;
  end process ;
 
  process
  begin
    L1A_fifo_empty < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    L1A_fifo_dout(15) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    L1A_fifo_dout(14) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    L1A_fifo_dout(13) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    L1A_fifo_dout(12) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    L1A_fifo_dout(11) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    L1A_fifo_dout(10) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    L1A_fifo_dout(9) < = '0';
    wait  for 169 ns;
    L1A_fifo_dout(9) < = '1';
    wait  for 9831 ns;
    wait ;
  end process ;
 
  process
  begin
    L1A_fifo_dout(8) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    L1A_fifo_dout(7) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    L1A_fifo_dout(6) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    L1A_fifo_dout(5) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    L1A_fifo_dout(4) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    L1A_fifo_dout(3) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    L1A_fifo_dout(2) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    L1A_fifo_dout(1) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    L1A_fifo_dout(0) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    L1A_fifo_rd_data_count(5) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    L1A_fifo_rd_data_count(4) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    L1A_fifo_rd_data_count(3) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    L1A_fifo_rd_data_count(2) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    L1A_fifo_rd_data_count(1) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    L1A_fifo_rd_data_count(0) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    L1A_fifo_wr_data_count(5) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    L1A_fifo_wr_data_count(4) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    L1A_fifo_wr_data_count(3) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    L1A_fifo_wr_data_count(2) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    L1A_fifo_wr_data_count(1) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    L1A_fifo_wr_data_count(0) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    T_request_fifo_empty < = '1';
    wait  for 58 ns;
    T_request_fifo_empty < = '0';
    wait  for 9942 ns;
    wait ;
  end process ;
 
  process
  begin
    T_request_fifo_dout(47) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    T_request_fifo_dout(46) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    T_request_fifo_dout(45) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    T_request_fifo_dout(44) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    T_request_fifo_dout(43) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    T_request_fifo_dout(42) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    T_request_fifo_dout(41) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    T_request_fifo_dout(40) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    T_request_fifo_dout(39) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    T_request_fifo_dout(38) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    T_request_fifo_dout(37) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    T_request_fifo_dout(36) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    T_request_fifo_dout(35) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    T_request_fifo_dout(34) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    T_request_fifo_dout(33) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    T_request_fifo_dout(32) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    T_request_fifo_dout(31) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    T_request_fifo_dout(30) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    T_request_fifo_dout(29) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    T_request_fifo_dout(28) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    T_request_fifo_dout(27) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    T_request_fifo_dout(26) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    T_request_fifo_dout(25) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    T_request_fifo_dout(24) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    T_request_fifo_dout(23) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    T_request_fifo_dout(22) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    T_request_fifo_dout(21) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    T_request_fifo_dout(20) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    T_request_fifo_dout(19) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    T_request_fifo_dout(18) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    T_request_fifo_dout(17) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    T_request_fifo_dout(16) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    T_request_fifo_dout(15) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    T_request_fifo_dout(14) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    T_request_fifo_dout(13) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    T_request_fifo_dout(12) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    T_request_fifo_dout(11) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    T_request_fifo_dout(10) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    T_request_fifo_dout(9) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    T_request_fifo_dout(8) < = '0';
    wait  for 58 ns;
    T_request_fifo_dout(8) < = '1';
    wait  for 9942 ns;
    wait ;
  end process ;
 
  process
  begin
    T_request_fifo_dout(7) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    T_request_fifo_dout(6) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    T_request_fifo_dout(5) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    T_request_fifo_dout(4) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    T_request_fifo_dout(3) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    T_request_fifo_dout(2) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    T_request_fifo_dout(1) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    T_request_fifo_dout(0) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    T_request_fifo_rd_data_empty(5) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    T_request_fifo_rd_data_empty(4) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    T_request_fifo_rd_data_empty(3) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    T_request_fifo_rd_data_empty(2) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    T_request_fifo_rd_data_empty(1) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    T_request_fifo_rd_data_empty(0) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    validate_ack < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    reject_ack < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    L1A_latency(15) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    L1A_latency(14) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    L1A_latency(13) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    L1A_latency(12) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    L1A_latency(11) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    L1A_latency(10) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    L1A_latency(9) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    L1A_latency(8) < = '0';
    wait  for 13 ns;
    L1A_latency(8) < = '1';
    wait  for 9987 ns;
    wait ;
  end process ;
 
  process
  begin
    L1A_latency(7) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    L1A_latency(6) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    L1A_latency(5) < = '0';
    wait  for 13 ns;
    L1A_latency(5) < = '1';
    wait  for 9987 ns;
    wait ;
  end process ;
 
  process
  begin
    L1A_latency(4) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    L1A_latency(3) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    L1A_latency(2) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    L1A_latency(1) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    L1A_latency(0) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    matching_window(15) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    matching_window(14) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    matching_window(13) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    matching_window(12) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    matching_window(11) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    matching_window(10) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    matching_window(9) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    matching_window(8) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    matching_window(7) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    matching_window(6) < = '0';
    wait  for 13 ns;
    matching_window(6) < = '1';
    wait  for 9987 ns;
    wait ;
  end process ;
 
  process
  begin
    matching_window(5) < = '0';
    wait  for 13 ns;
    matching_window(5) < = '1';
    wait  for 9987 ns;
    wait ;
  end process ;
 
  process
  begin
    matching_window(4) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    matching_window(3) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    matching_window(2) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    matching_window(1) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    matching_window(0) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    timestamp_lsw(15) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    timestamp_lsw(14) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    timestamp_lsw(13) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    timestamp_lsw(12) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    timestamp_lsw(11) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    timestamp_lsw(10) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    timestamp_lsw(9) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    timestamp_lsw(8) < = '0';
    wait  for 13 ns;
    timestamp_lsw(8) < = '1';
    wait  for 9987 ns;
    wait ;
  end process ;
 
  process
  begin
    timestamp_lsw(7) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    timestamp_lsw(6) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    timestamp_lsw(5) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    timestamp_lsw(4) < = '0';
    wait  for 13 ns;
    timestamp_lsw(4) < = '1';
    wait  for 9987 ns;
    wait ;
  end process ;
 
  process
  begin
    timestamp_lsw(3) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    timestamp_lsw(2) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    timestamp_lsw(1) < = '0';
    wait  for 10000 ns;
    wait ;
  end process ;
 
  process
  begin
    timestamp_lsw(0) < = '0';
    wait  for 13 ns;
    timestamp_lsw(0) < = '1';
    wait  for 9987 ns;
    wait ;
  end process ;
 
  process
  begin
    for wfe_i in 1 to 1000 loop
      gclk < = '0';
      wait  for 5 ns;
      gclk < = '1';
      wait  for 5 ns;
    end loop ;
    wait ;
  end process ;
 
end trigger_match;
 
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.NUMERIC_STD.all;
entity top_trigger_match is
end top_trigger_match;
 
use work.all;
architecture top of top_trigger_match is
 
  signal L1A_fifo_rd_en : std_logic;
  signal gclk : std_logic;
  signal reset : std_logic;
  signal L1A_fifo_empty : std_logic;
  signal T_request_fifo_rd_en : std_logic;
  signal L1A_fifo_dout : std_logic_vector(15 downto 0 );
  signal L1A_fifo_rd_data_count : std_logic_vector(5 downto 0 );
  signal L1A_fifo_wr_data_count : std_logic_vector(5 downto 0 );
  signal T_request_fifo_empty : std_logic;
  signal T_request_fifo_dout : std_logic_vector(47 downto 0 );
  signal T_request_fifo_rd_data_empty : std_logic_vector(5 downto 0 );
  signal validate : std_logic;
  signal rejecta : std_logic;
  signal validate_ack : std_logic;
  signal reject_ack : std_logic;
  signal L1A_latency : std_logic_vector(15 downto 0 );
  signal matching_window : std_logic_vector(15 downto 0 );
  signal timestamp_lsw : std_logic_vector(15 downto 0 );
  signal vaLreject_tag : std_logic_vector(47 downto 0 );
  component trigger_match
    port (
          L1A_fifo_rd_en : out std_logic;
          gclk : in std_logic;
          reset : in std_logic;
          L1A_fifo_empty : in std_logic;
          T_request_fifo_rd_en : out std_logic;
          L1A_fifo_dout : in std_logic_vector(15 downto 0 );
          L1A_fifo_rd_data_count : in std_logic_vector(5 downto 0 );
          L1A_fifo_wr_data_count : in std_logic_vector(5 downto 0 );
          T_request_fifo_empty : in std_logic;
          T_request_fifo_dout : in std_logic_vector(47 downto 0 );
          T_request_fifo_rd_data_empty : in std_logic_vector(5 downto 0 );
          validate : out std_logic;
          rejecta : out std_logic;
          validate_ack : in std_logic;
          reject_ack : in std_logic;
          L1A_latency : in std_logic_vector(15 downto 0 );
          matching_window : in std_logic_vector(15 downto 0 );
          timestamp_lsw : in std_logic_vector(15 downto 0 );
          vaLreject_tag : out std_logic_vector(47 downto 0 )
          );
  end component;
  component stim0
    port (
          L1A_fifo_rd_en : in std_logic;
          gclk : inout std_logic;
          reset : inout std_logic;
          L1A_fifo_empty : inout std_logic;
          T_request_fifo_rd_en : in std_logic;
          L1A_fifo_dout : inout std_logic_vector(15 downto 0 );
          L1A_fifo_rd_data_count : inout std_logic_vector(5 downto 0 );
          L1A_fifo_wr_data_count : inout std_logic_vector(5 downto 0 );
          T_request_fifo_empty : inout std_logic;
          T_request_fifo_dout : inout std_logic_vector(47 downto 0 );
          T_request_fifo_rd_data_empty : inout std_logic_vector(5 downto 0 );
          validate : in std_logic;
          rejecta : in std_logic;
          validate_ack : inout std_logic;
          reject_ack : inout std_logic;
          L1A_latency : inout std_logic_vector(15 downto 0 );
          matching_window : inout std_logic_vector(15 downto 0 );
          timestamp_lsw : inout std_logic_vector(15 downto 0 );
          vaLreject_tag : in std_logic_vector(47 downto 0 )
          );
  end component;
  -- Start Configuration Specification
  -- ++ for all : trigger_match
  -- ++     use entity work.trigger_match(trigger_match);
 
  -- ++ for all : stim0
  -- ++     use entity work.stim0(trigger_match);
  -- End Configuration Specification
 
begin
 
 
  trigger_match_inst : trigger_match
    port map (L1A_fifo_rd_en,
              gclk,
              reset,
              L1A_fifo_empty,
              T_request_fifo_rd_en,
              L1A_fifo_dout,
              L1A_fifo_rd_data_count,
              L1A_fifo_wr_data_count,
              T_request_fifo_empty,
              T_request_fifo_dout,
              T_request_fifo_rd_data_empty,
              validate,
              rejecta,
              validate_ack,
              reject_ack,
              L1A_latency,
              matching_window,
              timestamp_lsw,
              vaLreject_tag);
 
  stim0_inst : stim0
    port map (L1A_fifo_rd_en,
              gclk,
              reset,
              L1A_fifo_empty,
              T_request_fifo_rd_en,
              L1A_fifo_dout,
              L1A_fifo_rd_data_count,
              L1A_fifo_wr_data_count,
              T_request_fifo_empty,
              T_request_fifo_dout,
              T_request_fifo_rd_data_empty,
              validate,
              rejecta,
              validate_ack,
              reject_ack,
              L1A_latency,
              matching_window,
              timestamp_lsw,
              vaLreject_tag);
end top;