----------------------------------------------------
--  
--      VHDL code generated by Visual Elite
--
--  Root of Design:
--  ---------------
--      Unit    Name  :  GTS_top
--      Library Name  :  GTS
--  
--      Creation Date :  Thu Nov  3 13:16:42 2005
--      Version       :  3.8.3 build 14. Date: Aug  4 2005. License: 2005.8
--  
--  Options Used:
--  -------------
--      Target
--         Language   :  As Is
--         Purpose    :  Synthesis
--         Vendor     :  Synplify
--  
--      Style
--         Use Procedures                 :  No
--         Code Destination               :  Combined file
--         Attach Packages                :  Yes
--         Generate Entity                :  Yes
--         Attach Directives              :  Yes
--         Structural                     :  No
--         Configuration Specification    :  No
--         library name in
--         Configuration Specification    :  No
--         Configuration Declaration      :  None
--         Preserve spacing for free text :  Yes
--         Declaration alignment          :  No
--
----------------------------------------------------
----------------------------------------------------
--  
--  Library Name :  GTS
--  Unit    Name :  gts_pack
--  Unit    Type :  Package
--  
------------------------------------------------------
 -----------------------------------------------------------------------------
   -- This functional block provides the EDAC logic to correct up
   -- to one bit error and to detect up to two bit errors in an
   -- 4-bit input data word. The codewords are 8-bit long.
   -- It is a modified Hamming (8, 4, 4) code featuring
   -- Single Error Correction (SEC) and Double Error Detection (DED).
   --
   -- Two parity bits have been inversed to avoid an all-zero code word.
   -----------------------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;

package gts_pack is
   -----------------------------------------------------------------------------
   -- Generic data types, leftmost bit, number 0, is the most significant
   -----------------------------------------------------------------------------
   subtype Word4	 is std_logic_vector(0 to  3);
   subtype nb 		 is std_logic_vector(3 downto 0);
   type pl 		 is array (natural range < >) of nb;

-- Global downlink (ROOT --> Mezzanines) commands

   CONSTANT C_L1A	 : std_logic_vector(3 downto 0) := "0000";
   CONSTANT C_SRESET	 : std_logic_vector(3 downto 0) := "0001";
   CONSTANT C_SYNC	 : std_logic_vector(3 downto 0) := "0010";
   CONSTANT C_TRGPULSE	 : std_logic_vector(3 downto 0) := "0011";

-- Global uplink (Mezzanine --> ROOT) commands

   CONSTANT C_TRGREQ		 : std_logic_vector(7 downto 0) := "00000001";
   CONSTANT C_BACKPON		 : std_logic_vector(7 downto 0) := "00000010";
   CONSTANT C_BACKPOFF		 : std_logic_vector(7 downto 0) := "00000011";
   CONSTANT C_IDLE		 : std_logic_vector(7 downto 0) := "00000100";


end gts_pack;

----------------------------------------------------
--  
--  Library Name :  GTS
--  Unit    Name :  fifo_l1a
--  Unit    Type :  Text Unit
--  
------------------------------------------------------
--------------------------------------------------------------------------------
--     This file is owned and controlled by Xilinx and must be used           --
--     solely for design, simulation, implementation and creation of          --
--     design files limited to Xilinx devices or technologies. Use            --
--     with non-Xilinx devices or technologies is expressly prohibited        --
--     and immediately terminates your license.                               --
--                                                                            --
--     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"          --
--     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                --
--     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION        --
--     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION            --
--     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS              --
--     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                --
--     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE       --
--     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY               --
--     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                --
--     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR         --
--     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF        --
--     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS        --
--     FOR A PARTICULAR PURPOSE.                                              --
--                                                                            --
--     Xilinx products are not intended for use in life support               --
--     appliances, devices, or systems. Use in such applications are          --
--     expressly prohibited.                                                  --
--                                                                            --
--     (c) Copyright 1995-2005 Xilinx, Inc.                                   --
--     All rights reserved.                                                   --
--------------------------------------------------------------------------------
-- You must compile the wrapper file fifo_l1a.vhd when simulating
-- the core, fifo_l1a. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".

-- The synopsys directives "translate_off/translate_on" specified
-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synopsys translate_off
Library XilinxCoreLib;
-- synopsys translate_on
ENTITY fifo_l1a IS
	port (
	din: IN std_logic_VECTOR(39 downto 0);
	rd_clk: IN std_logic;
	rd_en: IN std_logic;
	rst: IN std_logic;
	wr_clk: IN std_logic;
	wr_en: IN std_logic;
	dout: OUT std_logic_VECTOR(39 downto 0);
	empty: OUT std_logic;
	full: OUT std_logic;
	rd_data_count: OUT std_logic_VECTOR(5 downto 0);
	wr_data_count: OUT std_logic_VECTOR(5 downto 0));
END fifo_l1a;



ARCHITECTURE fifo_l1a_a OF fifo_l1a IS
-- synopsys translate_off
component wrapped_fifo_l1a
	port (
	din: IN std_logic_VECTOR(39 downto 0);
	rd_clk: IN std_logic;
	rd_en: IN std_logic;
	rst: IN std_logic;
	wr_clk: IN std_logic;
	wr_en: IN std_logic;
	dout: OUT std_logic_VECTOR(39 downto 0);
	empty: OUT std_logic;
	full: OUT std_logic;
	rd_data_count: OUT std_logic_VECTOR(5 downto 0);
	wr_data_count: OUT std_logic_VECTOR(5 downto 0));
end component;

-- Configuration specification 
	for all : wrapped_fifo_l1a use entity XilinxCoreLib.fifo_generator_v2_2(behavioral)
		generic map(
			c_wr_response_latency => 1,
			c_has_rd_data_count => 1,
			c_din_width => 40,
			c_has_wr_data_count => 1,
			c_implementation_type => 2,
			c_family => "virtex2p",
			c_has_wr_rst => 0,
			c_underflow_low => 0,
			c_has_meminit_file => 0,
			c_has_overflow => 0,
			c_preload_latency => 1,
			c_dout_width => 40,
			c_rd_depth => 64,
			c_default_value => "BlankString",
			c_mif_file_name => "BlankString",
			c_has_underflow => 0,
			c_has_rd_rst => 0,
			c_has_almost_full => 0,
			c_has_rst => 1,
			c_data_count_width => 2,
			c_has_wr_ack => 0,
			c_wr_ack_low => 0,
			c_common_clock => 0,
			c_rd_pntr_width => 6,
			c_has_almost_empty => 0,
			c_rd_data_count_width => 6,
			c_enable_rlocs => 0,
			c_wr_pntr_width => 6,
			c_overflow_low => 0,
			c_prog_empty_type => 0,
			c_optimization_mode => 0,
			c_wr_data_count_width => 6,
			c_preload_regs => 0,
			c_dout_rst_val => "0",
			c_has_data_count => 0,
			c_prog_full_thresh_negate_val => 48,
			c_wr_depth => 64,
			c_prog_empty_thresh_negate_val => 16,
			c_prog_empty_thresh_assert_val => 16,
			c_has_valid => 0,
			c_init_wr_pntr_val => 0,
			c_prog_full_thresh_assert_val => 48,
			c_use_fifo16_flags => 0,
			c_has_backup => 0,
			c_valid_low => 0,
			c_prim_fifo_type => 512,
			c_count_type => 0,
			c_prog_full_type => 0,
			c_memory_type => 1);
-- synopsys translate_on
BEGIN
-- synopsys translate_off
U0 : wrapped_fifo_l1a
		port map (
			din => din,
			rd_clk => rd_clk,
			rd_en => rd_en,
			rst => rst,
			wr_clk => wr_clk,
			wr_en => wr_en,
			dout => dout,
			empty => empty,
			full => full,
			rd_data_count => rd_data_count,
			wr_data_count => wr_data_count);
-- synopsys translate_on

END fifo_l1a_a;



----------------------------------------------------
--  
--  Library Name :  GTS
--  Unit    Name :  dpram_tstamp
--  Unit    Type :  Text Unit
--  
------------------------------------------------------
--------------------------------------------------------------------------------
--     This file is owned and controlled by Xilinx and must be used           --
--     solely for design, simulation, implementation and creation of          --
--     design files limited to Xilinx devices or technologies. Use            --
--     with non-Xilinx devices or technologies is expressly prohibited        --
--     and immediately terminates your license.                               --
--                                                                            --
--     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"          --
--     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                --
--     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION        --
--     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION            --
--     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS              --
--     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                --
--     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE       --
--     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY               --
--     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                --
--     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR         --
--     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF        --
--     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS        --
--     FOR A PARTICULAR PURPOSE.                                              --
--                                                                            --
--     Xilinx products are not intended for use in life support               --
--     appliances, devices, or systems. Use in such applications are          --
--     expressly prohibited.                                                  --
--                                                                            --
--     (c) Copyright 1995-2005 Xilinx, Inc.                                   --
--     All rights reserved.                                                   --
--------------------------------------------------------------------------------
-- You must compile the wrapper file dpram_tstamp.vhd when simulating
-- the core, dpram_tstamp. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".

-- The synopsys directives "translate_off/translate_on" specified
-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).

-- synopsys translate_off
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

Library XilinxCoreLib;
ENTITY dpram_tstamp IS
	port (
	addra: IN std_logic_VECTOR(4 downto 0);
	addrb: IN std_logic_VECTOR(4 downto 0);
	clka: IN std_logic;
	clkb: IN std_logic;
	dina: IN std_logic_VECTOR(47 downto 0);
	dinb: IN std_logic_VECTOR(47 downto 0);
	doutb: OUT std_logic_VECTOR(47 downto 0);
	wea: IN std_logic;
	web: IN std_logic);
END dpram_tstamp;



ARCHITECTURE dpram_tstamp_a OF dpram_tstamp IS

component wrapped_dpram_tstamp
	port (
	addra: IN std_logic_VECTOR(4 downto 0);
	addrb: IN std_logic_VECTOR(4 downto 0);
	clka: IN std_logic;
	clkb: IN std_logic;
	dina: IN std_logic_VECTOR(47 downto 0);
	dinb: IN std_logic_VECTOR(47 downto 0);
	doutb: OUT std_logic_VECTOR(47 downto 0);
	wea: IN std_logic;
	web: IN std_logic);
end component;

-- Configuration specification 
	for all : wrapped_dpram_tstamp use entity XilinxCoreLib.blkmemdp_v6_2(behavioral)
		generic map(
			c_reg_inputsb => 0,
			c_reg_inputsa => 0,
			c_has_ndb => 0,
			c_has_nda => 0,
			c_ytop_addr => "1024",
			c_has_rfdb => 0,
			c_has_rfda => 0,
			c_ywea_is_high => 1,
			c_yena_is_high => 1,
			c_yclka_is_rising => 1,
			c_yhierarchy => "hierarchy1",
			c_ysinita_is_high => 1,
			c_ybottom_addr => "0",
			c_width_b => 48,
			c_width_a => 48,
			c_sinita_value => "0",
			c_sinitb_value => "0",
			c_limit_data_pitch => 18,
			c_write_modeb => 0,
			c_write_modea => 0,
			c_has_rdyb => 0,
			c_yuse_single_primitive => 0,
			c_has_rdya => 0,
			c_addra_width => 5,
			c_addrb_width => 5,
			c_has_limit_data_pitch => 0,
			c_default_data => "0",
			c_pipe_stages_b => 0,
			c_yweb_is_high => 1,
			c_yenb_is_high => 1,
			c_pipe_stages_a => 0,
			c_yclkb_is_rising => 1,
			c_yydisable_warnings => 1,
			c_enable_rlocs => 0,
			c_ysinitb_is_high => 1,
			c_has_default_data => 1,
			c_has_web => 1,
			c_has_sinitb => 0,
			c_has_wea => 1,
			c_has_sinita => 0,
			c_has_dinb => 1,
			c_has_dina => 1,
			c_ymake_bmm => 0,
			c_sim_collision_check => "NONE",
			c_has_enb => 0,
			c_has_ena => 0,
			c_depth_b => 32,
			c_mem_init_file => "g:\marco\GTS\mezzanine\dpram_tstamp\dpram_tstamp.mif",
			c_depth_a => 32,
			c_has_doutb => 1,
			c_has_douta => 0,
			c_yprimitive_type => "16kx1");
BEGIN

U0 : wrapped_dpram_tstamp
		port map (
			addra => addra,
			addrb => addrb,
			clka => clka,
			clkb => clkb,
			dina => dina,
			dinb => dinb,
			doutb => doutb,
			wea => wea,
			web => web);
END dpram_tstamp_a;

-- synopsys translate_on



----------------------------------------------------
--  
--  Library Name :  GTS
--  Unit    Name :  fifo_freelist
--  Unit    Type :  Text Unit
--  
------------------------------------------------------
--------------------------------------------------------------------------------
--     This file is owned and controlled by Xilinx and must be used           --
--     solely for design, simulation, implementation and creation of          --
--     design files limited to Xilinx devices or technologies. Use            --
--     with non-Xilinx devices or technologies is expressly prohibited        --
--     and immediately terminates your license.                               --
--                                                                            --
--     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"          --
--     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                --
--     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION        --
--     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION            --
--     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS              --
--     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                --
--     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE       --
--     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY               --
--     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                --
--     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR         --
--     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF        --
--     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS        --
--     FOR A PARTICULAR PURPOSE.                                              --
--                                                                            --
--     Xilinx products are not intended for use in life support               --
--     appliances, devices, or systems. Use in such applications are          --
--     expressly prohibited.                                                  --
--                                                                            --
--     (c) Copyright 1995-2005 Xilinx, Inc.                                   --
--     All rights reserved.                                                   --
--------------------------------------------------------------------------------
-- You must compile the wrapper file fifo_freelist.vhd when simulating
-- the core, fifo_freelist. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".

-- The synopsys directives "translate_off/translate_on" specified
-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).

-- synopsys translate_off
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

Library XilinxCoreLib;
ENTITY fifo_freelist IS
	port (
	din: IN std_logic_VECTOR(4 downto 0);
	rd_clk: IN std_logic;
	rd_en: IN std_logic;
	rst: IN std_logic;
	wr_clk: IN std_logic;
	wr_en: IN std_logic;
	dout: OUT std_logic_VECTOR(4 downto 0);
	empty: OUT std_logic;
	full: OUT std_logic;
	wr_data_count: OUT std_logic_VECTOR(4 downto 0));
END fifo_freelist;



ARCHITECTURE fifo_freelist_a OF fifo_freelist IS

component wrapped_fifo_freelist
	port (
	din: IN std_logic_VECTOR(4 downto 0);
	rd_clk: IN std_logic;
	rd_en: IN std_logic;
	rst: IN std_logic;
	wr_clk: IN std_logic;
	wr_en: IN std_logic;
	dout: OUT std_logic_VECTOR(4 downto 0);
	empty: OUT std_logic;
	full: OUT std_logic;
	wr_data_count: OUT std_logic_VECTOR(4 downto 0));
end component;

-- Configuration specification 
	for all : wrapped_fifo_freelist use entity XilinxCoreLib.fifo_generator_v2_1(behavioral)
		generic map(
			c_wr_response_latency => 1,
			c_has_rd_data_count => 0,
			c_din_width => 5,
			c_has_wr_data_count => 1,
			c_implementation_type => 2,
			c_family => "virtex2p",
			c_has_wr_rst => 0,
			c_underflow_low => 0,
			c_has_meminit_file => 0,
			c_has_overflow => 0,
			c_preload_latency => 0,
			c_dout_width => 5,
			c_rd_depth => 32,
			c_default_value => "BlankString",
			c_mif_file_name => "BlankString",
			c_has_underflow => 0,
			c_has_rd_rst => 0,
			c_has_almost_full => 0,
			c_has_rst => 1,
			c_data_count_width => 2,
			c_has_wr_ack => 0,
			c_wr_ack_low => 0,
			c_common_clock => 0,
			c_rd_pntr_width => 5,
			c_has_almost_empty => 0,
			c_rd_data_count_width => 5,
			c_enable_rlocs => 0,
			c_wr_pntr_width => 5,
			c_overflow_low => 0,
			c_prog_empty_type => 0,
			c_optimization_mode => 0,
			c_wr_data_count_width => 5,
			c_preload_regs => 1,
			c_dout_rst_val => "0",
			c_has_data_count => 0,
			c_prog_full_thresh_negate_val => 24,
			c_wr_depth => 32,
			c_prog_empty_thresh_negate_val => 8,
			c_prog_empty_thresh_assert_val => 8,
			c_has_valid => 0,
			c_init_wr_pntr_val => 0,
			c_prog_full_thresh_assert_val => 24,
			c_has_backup => 0,
			c_valid_low => 0,
			c_prim_fifo_type => 512,
			c_count_type => 0,
			c_prog_full_type => 0,
			c_memory_type => 1);
BEGIN

U0 : wrapped_fifo_freelist
		port map (
			din => din,
			rd_clk => rd_clk,
			rd_en => rd_en,
			rst => rst,
			wr_clk => wr_clk,
			wr_en => wr_en,
			dout => dout,
			empty => empty,
			full => full,
			wr_data_count => wr_data_count);
END fifo_freelist_a;

-- synopsys translate_on



----------------------------------------------------
--  
--  Library Name :  GTS
--  Unit    Name :  T_request_ctrl
--  Unit    Type :  State Machine
--  
------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
 
 
entity T_request_ctrl is
  port (
        T_request_mem_full : in std_logic;
        trigger_request : in std_logic_vector(1 downto 0 );
        T_request_mem_wr_en : out std_logic;
        gclk : in std_logic;
        reset : in std_logic;
        timestamp : in std_logic_vector(47 downto 0 );
        t : out std_logic_vector(47 downto 0 );
        rd_en : out std_logic;
        T_request_wr_data_count : in std_logic_vector(4 downto 0 );
        lt_strobe : out std_logic;
        ltrg : out std_logic_vector(1 downto 0 );
        ltag : out std_logic_vector(7 downto 0 )
        );
 
end T_request_ctrl;
 
 
architecture T_request_ctrl of T_request_ctrl is
 
  signal tstamp : std_logic_vector(47 downto 0 );
 
  type visual_S0_states is (S0, S1, S2, S3, S4, S5, S6, S7, S9);
  signal visual_S0_current : visual_S0_states;
 
 
begin
 
 
 
  -- Synchronous process
  T_request_ctrl_S0:
  process (gclk)
  begin
 
    if (gclk'event and gclk = '1') then
      if (reset = '1') then
        T_request_mem_wr_en< ='0';
        ltag< =(others=>'0');
        ltrg< ="00";
        lt_strobe< ='0';
        t< =(others=>'0');
        visual_S0_current < = S0;
      else
 
        case visual_S0_current is
          when S0 =>
            if (trigger_request = "01" and T_request_mem_full = '0') then
              tstamp< =timestamp(47 downto 0);
              rd_en < = '1';
              visual_S0_current < = S9;
            else
              visual_S0_current < = S0;
            end if;
 
          when S1 =>
            ltrg< ="00";
            T_request_mem_wr_en< ='0';
            ltag< =tstamp(47 downto 40);
            lt_strobe< ='1';
            visual_S0_current < = S2;
 
          when S2 =>
            ltag< =tstamp(39 downto 32);
            visual_S0_current < = S3;
 
          when S3 =>
            ltag< =tstamp(31 downto 24);
            visual_S0_current < = S4;
 
          when S4 =>
            ltag< =tstamp(23 downto 16);
            visual_S0_current < = S5;
 
          when S5 =>
            ltag< =tstamp(15 downto 8);
            visual_S0_current < = S6;
 
          when S6 =>
            ltag< =tstamp(7 downto 0);
            visual_S0_current < = S7;
 
          when S7 =>
            T_request_mem_wr_en< ='0';
            ltag< =(others=>'0');
            ltrg< ="00";
            lt_strobe< ='0';
            t< =(others=>'0');
            visual_S0_current < = S0;
 
          when S9 =>
            ltrg< ="01";
            T_request_mem_wr_en< ='1';
            t< =tstamp;
            rd_en < = '0';
            visual_S0_current < = S1;
 
          when others =>
 
            T_request_mem_wr_en< ='0';
            ltag< =(others=>'0');
            ltrg< ="00";
            lt_strobe< ='0';
            t< =(others=>'0');
            visual_S0_current < = S0;
        end case;
      end if;
    end if;
  end process T_request_ctrl_S0;
 
end T_request_ctrl;
----------------------------------------------------
--  
--  Library Name :  GTS
--  Unit    Name :  lut_b
--  Unit    Type :  Text Unit
--  
------------------------------------------------------
--------------------------------------------------------------------------------
--     This file is owned and controlled by Xilinx and must be used           --
--     solely for design, simulation, implementation and creation of          --
--     design files limited to Xilinx devices or technologies. Use            --
--     with non-Xilinx devices or technologies is expressly prohibited        --
--     and immediately terminates your license.                               --
--                                                                            --
--     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"          --
--     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                --
--     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION        --
--     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION            --
--     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS              --
--     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                --
--     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE       --
--     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY               --
--     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                --
--     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR         --
--     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF        --
--     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS        --
--     FOR A PARTICULAR PURPOSE.                                              --
--                                                                            --
--     Xilinx products are not intended for use in life support               --
--     appliances, devices, or systems. Use in such applications are          --
--     expressly prohibited.                                                  --
--                                                                            --
--     (c) Copyright 1995-2005 Xilinx, Inc.                                   --
--     All rights reserved.                                                   --
--------------------------------------------------------------------------------
-- You must compile the wrapper file lut_b.vhd when simulating
-- the core, lut_b. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".

-- The synopsys directives "translate_off/translate_on" specified
-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synopsys translate_off
Library XilinxCoreLib;
-- synopsys translate_on
ENTITY lut_b IS
	port (
	A: IN std_logic_VECTOR(3 downto 0);
	SPO: OUT std_logic_VECTOR(47 downto 0));
END lut_b;



ARCHITECTURE lut_b_a OF lut_b IS
-- synopsys translate_off
component wrapped_lut_b
	port (
	A: IN std_logic_VECTOR(3 downto 0);
	SPO: OUT std_logic_VECTOR(47 downto 0));
end component;

-- Configuration specification 
	for all : wrapped_lut_b use entity XilinxCoreLib.C_DIST_MEM_V7_1(behavioral)
		generic map(
			c_qualify_we => 0,
			c_mem_type => 0,
			c_has_qdpo_rst => 0,
			c_has_qspo => 0,
			c_has_qspo_rst => 0,
			c_has_dpo => 0,
			c_has_qdpo_clk => 0,
			c_has_d => 0,
			c_qce_joined => 0,
			c_width => 48,
			c_reg_a_d_inputs => 0,
			c_latency => 0,
			c_has_spo => 1,
			c_has_we => 0,
			c_depth => 16,
			c_has_i_ce => 0,
			c_default_data_radix => 1,
			c_default_data => "0",
			c_has_dpra => 0,
			c_has_clk => 0,
			c_enable_rlocs => 1,
			c_generate_mif => 1,
			c_has_qspo_ce => 0,
			c_addr_width => 4,
			c_has_qdpo_srst => 0,
			c_mux_type => 0,
			c_has_spra => 0,
			c_has_qdpo => 0,
			c_mem_init_file => "/disk1/users/bellato/GTS/Mezzanine/rom16x48_2/lut_b/lut_b.mif",
			c_reg_dpra_input => 0,
			c_has_qspo_srst => 0,
			c_has_rd_en => 0,
			c_read_mif => 1,
			c_sync_enable => 0,
			c_has_qdpo_ce => 0);
-- synopsys translate_on
BEGIN
-- synopsys translate_off
U0 : wrapped_lut_b
		port map (
			A => A,
			SPO => SPO);
-- synopsys translate_on

END lut_b_a;



----------------------------------------------------
--  
--  Library Name :  GTS
--  Unit    Name :  lut_a
--  Unit    Type :  Text Unit
--  
------------------------------------------------------
--------------------------------------------------------------------------------
--     This file is owned and controlled by Xilinx and must be used           --
--     solely for design, simulation, implementation and creation of          --
--     design files limited to Xilinx devices or technologies. Use            --
--     with non-Xilinx devices or technologies is expressly prohibited        --
--     and immediately terminates your license.                               --
--                                                                            --
--     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"          --
--     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                --
--     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION        --
--     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION            --
--     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS              --
--     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                --
--     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE       --
--     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY               --
--     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                --
--     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR         --
--     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF        --
--     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS        --
--     FOR A PARTICULAR PURPOSE.                                              --
--                                                                            --
--     Xilinx products are not intended for use in life support               --
--     appliances, devices, or systems. Use in such applications are          --
--     expressly prohibited.                                                  --
--                                                                            --
--     (c) Copyright 1995-2005 Xilinx, Inc.                                   --
--     All rights reserved.                                                   --
--------------------------------------------------------------------------------
-- You must compile the wrapper file lut_a.vhd when simulating
-- the core, lut_a. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".

-- The synopsys directives "translate_off/translate_on" specified
-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synopsys translate_off
Library XilinxCoreLib;
-- synopsys translate_on
ENTITY lut_a IS
	port (
	A: IN std_logic_VECTOR(3 downto 0);
	SPO: OUT std_logic_VECTOR(47 downto 0));
END lut_a;



ARCHITECTURE lut_a_a OF lut_a IS
-- synopsys translate_off
component wrapped_lut_a
	port (
	A: IN std_logic_VECTOR(3 downto 0);
	SPO: OUT std_logic_VECTOR(47 downto 0));
end component;

-- Configuration specification 
	for all : wrapped_lut_a use entity XilinxCoreLib.C_DIST_MEM_V7_1(behavioral)
		generic map(
			c_qualify_we => 0,
			c_mem_type => 0,
			c_has_qdpo_rst => 0,
			c_has_qspo => 0,
			c_has_qspo_rst => 0,
			c_has_dpo => 0,
			c_has_qdpo_clk => 0,
			c_has_d => 0,
			c_qce_joined => 0,
			c_width => 48,
			c_reg_a_d_inputs => 0,
			c_latency => 0,
			c_has_spo => 1,
			c_has_we => 0,
			c_depth => 16,
			c_has_i_ce => 0,
			c_default_data_radix => 1,
			c_default_data => "0",
			c_has_dpra => 0,
			c_has_clk => 0,
			c_enable_rlocs => 1,
			c_generate_mif => 1,
			c_has_qspo_ce => 0,
			c_addr_width => 4,
			c_has_qdpo_srst => 0,
			c_mux_type => 0,
			c_has_spra => 0,
			c_has_qdpo => 0,
			c_mem_init_file => "/disk1/users/bellato/GTS/Mezzanine/rom16x48_1/lut_a/lut_a.mif",
			c_reg_dpra_input => 0,
			c_has_qspo_srst => 0,
			c_has_rd_en => 0,
			c_read_mif => 1,
			c_sync_enable => 0,
			c_has_qdpo_ce => 0);
-- synopsys translate_on
BEGIN
-- synopsys translate_off
U0 : wrapped_lut_a
		port map (
			A => A,
			SPO => SPO);
-- synopsys translate_on

END lut_a_a;



----------------------------------------------------
--  
--  Library Name :  GTS
--  Unit    Name :  auto_ctrl
--  Unit    Type :  State Machine
--  
------------------------------------------------------
 
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.STD_LOGIC_SIGNED.all;
use ieee.NUMERIC_STD.all;
library synplify;
use synplify.attributes.all;
 
 
entity auto_ctrl is
  port (
        bclk : in std_logic;
        lreset : in std_logic;
        a_ack : in std_logic;
        a_idle : out std_logic;
        a_comma : out std_logic;
        TERCNT : in std_logic;
        hun : in std_logic
        );
 
end auto_ctrl;
 
 
architecture auto_ctrl of auto_ctrl is
 
  type visual_S0_states is (S0, S1, S2);
  signal visual_S0_current : visual_S0_states;
 
 
begin
 
 
 
  -- Synchronous process
  auto_ctrl_S0:
  process (bclk, lreset)
  begin
 
    if (lreset = '1') then
      a_idle< ='0';
      a_comma< ='0';
      visual_S0_current < = S0;
    elsif (bclk'event and bclk = '1') then
 
      case visual_S0_current is
        when S0 =>
          if (tercnt = '1') then
            a_idle< ='1';
            visual_S0_current < = S2;
          elsif (hun = '1') then
            a_comma< ='1';
            visual_S0_current < = S1;
          else
            visual_S0_current < = S0;
          end if;
 
        when S1 =>
          if (a_ack = '1') then
            a_idle< ='0';
            a_comma< ='0';
            visual_S0_current < = S0;
          else
            visual_S0_current < = S1;
          end if;
 
        when S2 =>
          if (a_ack = '1') then
            a_idle< ='0';
            a_comma< ='0';
            visual_S0_current < = S0;
          else
            visual_S0_current < = S2;
          end if;
 
        when others =>
 
          a_idle< ='0';
          a_comma< ='0';
          visual_S0_current < = S0;
      end case;
    end if;
  end process auto_ctrl_S0;
 
end auto_ctrl;
----------------------------------------------------
--  
--  Library Name :  GTS
--  Unit    Name :  auto_cmd
--  Unit    Type :  Block Diagram
--  
------------------------------------------------------
 
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.STD_LOGIC_SIGNED.all;
use ieee.NUMERIC_STD.all;
library synplify;
use synplify.attributes.all;
 
 
entity auto_cmd is
  port (
        a_comma : out std_logic;
        bclk : in std_logic;
        lreset : in std_logic;
        clear_idle : in std_logic;
        a_ack : in std_logic;
        a_idle : out std_logic
        );
 
 
end auto_cmd;
 
 
use work.all;
architecture auto_cmd of auto_cmd is
 
  signal O : std_logic;
  signal c_100 : std_logic_vector(6 downto 0 );
  signal hun : std_logic;
  signal CNT : std_logic_vector(6 downto 0 );
  signal c_126 : std_logic_vector(6 downto 0 );
  signal TERCNT : std_logic;
  component auto_ctrl
      port (
            bclk : in std_logic;
            lreset : in std_logic;
            a_ack : in std_logic;
            a_idle : out std_logic;
            a_comma : out std_logic;
            TERCNT : in std_logic;
            hun : in std_logic
            );
  end component;
  signal visual_C9_cur_state : std_logic_vector(7 - 1 downto 0 );
  signal visual_C9_next_state : std_logic_vector(7 - 1 downto 0 );
  signal visual_C9_next_count : std_logic_vector(7 - 1 downto 0 );
  signal visual_C9_en_state : std_logic_vector(7 - 1 downto 0 );
 
  -- Start Configuration Specification
  -- ++ for all : auto_ctrl use entity work.auto_ctrl(auto_ctrl);
  -- End Configuration Specification
 
begin
 
  inst_auto_ctrl: auto_ctrl
    port map (
              bclk => bclk,
              lreset => lreset,
              a_ack => a_ack,
              a_idle => a_idle,
              a_comma => a_comma,
              TERCNT => TERCNT,
              hun => hun
              );
 
      O < = '1';
 
  c_100(6 downto 0) < = "1100100";
 
 
 
  process (c_100 , CNT)
   begin
      if ((c_100(6 downto 0)) = (CNT(6 downto 0))) then
        hun < = '1';
      else
        hun < = '0';
      end if;
  end process;
 
 
 
  process (CNT , c_126)
   begin
      if ((CNT(6 downto 0)) = (c_126(6 downto 0))) then
        TERCNT < = '1';
      else
        TERCNT < = '0';
      end if;
  end process;
 
 
 
  CNT(6 downto 0) < = (visual_C9_cur_state);
 
 
  visual_C9_en_state < = visual_C9_next_count
                       when O = '1'
                       else visual_C9_cur_state;
 
  visual_C9_next_state < = visual_C9_en_state;
 
  process (bclk , lreset)
  begin
   if (lreset = '1') then
      visual_C9_cur_state < = (others => '0');
   elsif (bclk'event and bclk = '1') then
    if (clear_idle = '1') then
       visual_C9_cur_state < = (others => '1');
    else
 
       visual_C9_cur_state < = visual_C9_next_state;
   end if;
  end if;
  end process;
 
  process (visual_C9_cur_state )
  variable plus_minus_one : unsigned(7 - 1 downto 0);
 
  begin
    plus_minus_one :=  "0000001" ;
    visual_C9_next_count < = std_logic_vector(unsigned(visual_C9_cur_state) + plus_minus_one);
 
  end process;
 
 
  c_126(6 downto 0) < = "1111110";
 
end auto_cmd;
----------------------------------------------------
--  
--  Library Name :  GTS
--  Unit    Name :  L1A_fifo_ctrl
--  Unit    Type :  State Machine
--  
------------------------------------------------------
 
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.STD_LOGIC_SIGNED.all;
use ieee.NUMERIC_STD.all;
library synplify;
use synplify.attributes.all;
 
 
entity L1A_fifo_ctrl is
  port (
        bclk : in std_logic;
        lreset : in std_logic;
        L1A_fifo_wr_en : out std_logic;
        L1A_fifo_full : in std_logic;
        L1A_arrived : in std_logic
        );
 
end L1A_fifo_ctrl;
 
 
architecture L1A_fifo_ctrl of L1A_fifo_ctrl is
 
  type visual_S0_states is (S0, S1);
  signal visual_S0_current : visual_S0_states;
 
 
begin
 
 
 
  -- Synchronous process
  L1A_fifo_ctrl_S0:
  process (bclk, lreset)
  begin
 
    if (lreset = '1') then
      L1A_fifo_wr_en< ='0';
      visual_S0_current < = S0;
    elsif (bclk'event and bclk = '1') then
 
      case visual_S0_current is
        when S0 =>
          if (L1A_arrived = '1' and L1A_fifo_full = '0') then
            L1A_fifo_wr_en< ='1';
            visual_S0_current < = S1;
          else
            visual_S0_current < = S0;
          end if;
 
        when S1 =>
          L1A_fifo_wr_en< ='0';
          visual_S0_current < = S0;
 
        when others =>
 
          L1A_fifo_wr_en< ='0';
          visual_S0_current < = S0;
      end case;
    end if;
  end process L1A_fifo_ctrl_S0;
 
end L1A_fifo_ctrl;
----------------------------------------------------
--  
--  Library Name :  GTS
--  Unit    Name :  backp_ctrl
--  Unit    Type :  State Machine
--  
------------------------------------------------------
 
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.STD_LOGIC_SIGNED.all;
use ieee.NUMERIC_STD.all;
library synplify;
use synplify.attributes.all;
 
 
entity backp_ctrl is
  port (
        backpressure : in std_logic;
        bclk : in std_logic;
        lreset : in std_logic;
        bp_start : out std_logic;
        bp_stop : out std_logic;
        bp_ack : in std_logic
        );
 
end backp_ctrl;
 
 
architecture backp_ctrl of backp_ctrl is
 
  type visual_S0_states is (S0, S1, S2, S3);
  signal visual_S0_current : visual_S0_states;
 
 
begin
 
 
 
  -- Synchronous process
  backp_ctrl_S0:
  process (bclk, lreset)
  begin
 
    if (lreset = '1') then
      bp_stop< ='0';
      bp_start< ='0';
      visual_S0_current < = S0;
    elsif (bclk'event and bclk = '1') then
 
      case visual_S0_current is
        when S0 =>
          if (backpressure = '1') then
            bp_start< ='1';
            visual_S0_current < = S1;
          else
            visual_S0_current < = S0;
          end if;
 
        when S1 =>
          if (bp_ack = '1') then
            bp_start< ='0';
            visual_S0_current < = S3;
          else
            visual_S0_current < = S1;
          end if;
 
        when S2 =>
          if (bp_ack = '1') then
            bp_stop< ='0';
            bp_start< ='0';
            visual_S0_current < = S0;
          else
            visual_S0_current < = S2;
          end if;
 
        when S3 =>
          if (backpressure = '0') then
            bp_stop< ='1';
            visual_S0_current < = S2;
          else
            visual_S0_current < = S3;
          end if;
 
        when others =>
 
          bp_stop< ='0';
          bp_start< ='0';
          visual_S0_current < = S0;
      end case;
    end if;
  end process backp_ctrl_S0;
 
end backp_ctrl;
----------------------------------------------------
--  
--  Library Name :  GTS
--  Unit    Name :  Hamming8
--  Unit    Type :  Text Unit
--  
------------------------------------------------------
 -----------------------------------------------------------------------------
   -- This functional block provides the EDAC logic to correct up
   -- to one bit error and to detect up to two bit errors in an
   -- 4-bit input data word. The codewords are 8-bit long.
   -- It is a modified Hamming (8, 4, 4) code featuring
   -- Single Error Correction (SEC) and Double Error Detection (DED).
   --
   -- Two parity bits have been inversed to avoid an all-zero code word.
   -----------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;

entity Hamming8 is
   port(
      DataOut:       in    std_logic_vector(0 to 7) ;               -- Output data bits
      CheckOut:      out   std_logic_vector(0 to 7) ;               -- Output check bits

      DataIn:        in    std_logic_vector(0 to 7) ;               -- Input data bits
      CheckIn:       in    std_logic_vector(0 to 7) ;               -- Input check bits

      DataCorr:      out   std_logic_vector(0 to 7) ;               -- Corrected data bits
      SingleErr:     out   Std_ULogic;          -- Single error
      DoubleErr:     out   Std_ULogic;          -- Double error
      MultipleErr:   out   Std_ULogic          -- Uncorrectable error
   );
end Hamming8;



architecture RTL of Hamming8 is

 begin

   process (DataOut,DataIn,CheckIn)
      variable PgenL,PgenH:         Std_Logic_Vector(0 to 3);  -- Generated parity
      variable SyndL,SyndH:         Std_Logic_Vector(0 to 3);  -- Syndrome
      variable FlipL,FlipH:         Std_Logic_Vector(0 to 3);  -- Bits to invert
      variable ChipL,ChipH:         Std_Logic_Vector(0 to 3);  -- Errors in parity

   begin
      -- Check bit generator
      PgenL(0) := not (DataIn(0) xor DataIn(1) xor DataIn(2));
      PgenL(1) :=      DataIn(0) xor DataIn(1) xor DataIn(3);
      PgenL(2) := not (DataIn(0) xor DataIn(2) xor DataIn(3));
      PgenL(3) :=      DataIn(1) xor DataIn(2) xor DataIn(3);

      PgenH(0) := not (DataIn(4) xor DataIn(5) xor DataIn(6));
      PgenH(1) :=      DataIn(4) xor DataIn(5) xor DataIn(7);
      PgenH(2) := not (DataIn(4) xor DataIn(6) xor DataIn(7));
      PgenH(3) :=      DataIn(5) xor DataIn(6) xor DataIn(7);

      -- Syndrome bit generator
      SyndL(0) := PgenL(0) xor not CheckIn(0);
      SyndL(1) := PgenL(1) xor not CheckIn(1);
      SyndL(2) := PgenL(2) xor     CheckIn(2);
      SyndL(3) := PgenL(3) xor     CheckIn(3);

      SyndH(0) := PgenH(0) xor not CheckIn(4);
      SyndH(1) := PgenH(1) xor not CheckIn(5);
      SyndH(2) := PgenH(2) xor     CheckIn(6);
      SyndH(3) := PgenH(3) xor     CheckIn(7);

      -- Bit corrector
      if SyndL="1110" then
         FlipL(0) := '1';
      else
         FlipL(0) := '0';
      end if;
      if SyndL="1101" then
         FlipL(1) := '1';
      else
         FlipL(1) := '0';
      end if;
      if SyndL="1011" then
         FlipL(2) := '1';
      else
         FlipL(2) := '0';
      end if;
      if SyndL="0111" then
         FlipL(3) := '1';
      else
         FlipL(3) := '0';
      end if;

      if SyndH="1110" then
         FlipH(0) := '1';
      else
         FlipH(0) := '0';
      end if;
      if SyndH="1101" then
         FlipH(1) := '1';
      else
         FlipH(1) := '0';
      end if;
      if SyndH="1011" then
         FlipH(2) := '1';
      else
         FlipH(2) := '0';
      end if;
      if SyndH="0111" then
         FlipH(3) := '1';
      else
         FlipH(3) := '0';
      end if;

      -- Single error in check bits
      if SyndL="0001" then
         ChipL(0) := '1';
      else
         ChipL(0) := '0';
      end if;
      if SyndL="0010" then
         ChipL(1) := '1';
      else
         ChipL(1) := '0';
      end if;
      if SyndL="0100" then
         ChipL(2) := '1';
      else
         ChipL(2) := '0';
      end if;
      if SyndL="1000" then
         ChipL(3) := '1';
      else
         ChipL(3) := '0';
      end if;

      if SyndH="0001" then
         ChipH(0) := '1';
      else
         ChipH(0) := '0';
      end if;
      if SyndH="0010" then
         ChipH(1) := '1';
      else
         ChipH(1) := '0';
      end if;
      if SyndH="0100" then
         ChipH(2) := '1';
      else
         ChipH(2) := '0';
      end if;
      if SyndH="1000" then
         ChipH(3) := '1';
      else
         ChipH(3) := '0';
      end if;

      -- Corrected data
      DataCorr(0) < = DataIn(0) xor FlipL(0);
      DataCorr(1) < = DataIn(1) xor FlipL(1);
      DataCorr(2) < = DataIn(2) xor FlipL(2);
      DataCorr(3) < = DataIn(3) xor FlipL(3);

      DataCorr(4) < = DataIn(4) xor FlipH(0);
      DataCorr(5) < = DataIn(5) xor FlipH(1);
      DataCorr(6) < = DataIn(6) xor FlipH(2);
      DataCorr(7) < = DataIn(7) xor FlipH(3);

      -- Check bits
      CheckOut(0) < = not (not (DataOut(0) xor DataOut(1) xor DataOut(2)));
      CheckOut(1) < = not (     DataOut(0) xor DataOut(1) xor DataOut(3));
      CheckOut(2) < =     (not (DataOut(0) xor DataOut(2) xor DataOut(3)));
      CheckOut(3) < =     (     DataOut(1) xor DataOut(2) xor DataOut(3));

      CheckOut(4) < = not (not (DataOut(4) xor DataOut(5) xor DataOut(6)));
      CheckOut(5) < = not (     DataOut(4) xor DataOut(5) xor DataOut(7));
      CheckOut(6) < =     (not (DataOut(4) xor DataOut(6) xor DataOut(7)));
      CheckOut(7) < =     (     DataOut(5) xor DataOut(6) xor DataOut(7));

      -- Single correctable error flag
      SingleErr   < = (FlipL(0) or FlipL(1) or FlipL(2) or FlipL(3)) xor
                     (FlipH(0) or FlipH(1) or FlipH(2) or FlipH(3)) xor
                     (ChipL(0) or ChipL(1) or ChipL(2) or ChipL(3)) xor
                     (ChipH(0) or ChipH(1) or ChipH(2) or ChipH(3));

      -- double correctable error flag
      DoubleErr   < = ((FlipL(0) or FlipL(1) or FlipL(2) or FlipL(3)) or
                      (ChipL(0) or ChipL(1) or ChipL(2) or ChipL(3))) and

                     ((FlipH(0) or FlipH(1) or FlipH(2) or FlipH(3)) or
                      (ChipH(0) or ChipH(1) or ChipH(2) or ChipH(3)));

      -- Uncorrectable error flag
      if SyndL="0011" or SyndL="0101" or
         SyndL="0110" or SyndL="1001" or
         SyndL="1010" or SyndL="1100" or
         SyndL="1111" or
         SyndH="0011" or SyndH="0101" or
         SyndH="0110" or SyndH="1001" or
         SyndH="1010" or SyndH="1100" or
         SyndH="1111" then
         MultipleErr    < = '1';
      else
         MultipleErr    < = '0';
      end if;

   end process;
 end RTL;



----------------------------------------------------
--  
--  Library Name :  GTS
--  Unit    Name :  ctrl
--  Unit    Type :  State Machine
--  
------------------------------------------------------
 
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.STD_LOGIC_SIGNED.all;
use ieee.NUMERIC_STD.all;
library GTS;
use GTS.gts_pack.all;
library synplify;
use synplify.attributes.all;
 
 
entity ctrl is
  port (
        msg_in : in std_logic_vector(7 downto 0 );
        msg_strobe : in std_logic_vector(1 downto 0 );
        bclk : in std_logic;
        lreset : in std_logic;
        tag : in std_logic_vector(15 downto 0 );
        strobe : in std_logic;
        ack : out std_logic;
        DataOut : out std_logic_vector(0 to 7 );
        ts_16 : in std_logic_vector(15 downto 0 );
        a_idle : in std_logic;
        a_comma : in std_logic;
        a_ack : out std_logic;
        bp_ack : out std_logic;
        bp_stop : in std_logic;
        bp_start : in std_logic
        );
 
end ctrl;
 
 
architecture ctrl of ctrl is
 
  type visual_S0_states is (S0, S2, S17, S9, S10, S16, S19, S3, S4, S11, S12,
                            S13, S14, S15, S1, S5, S6, S7, S8);
  signal visual_S0_current : visual_S0_states;
 
 
begin
 
 
 
  -- Synchronous process
  ctrl_S0:
  process (bclk, lreset)
  begin
 
    if (lreset = '1') then
      DataOut< =(others =>'0');
      ack< ='0';
      a_ack< ='0';
      bp_ack< ='0';
      visual_S0_current < = S0;
    elsif (bclk'event and bclk = '1') then
 
      case visual_S0_current is
        when S0 =>
          if (bp_start = '1') then
            DataOut(0 to 3)< ="1111"; -- start of cmd
            DataOut(4 to 7)< ="0001"; -- cmd length
            visual_S0_current < = S10;
          elsif (bp_stop = '1') then
            DataOut(0 to 3)< ="1111"; -- start of cmd
            DataOut(4 to 7)< ="0001"; -- cmd length
            visual_S0_current < = S2;
          elsif (strobe = '1') then
            DataOut(0 to 3)< ="1111"; -- start of cmd
            DataOut(4 to 7)< ="0011"; -- cmd length
            visual_S0_current < = S1;
          elsif (a_idle = '1') then
            DataOut(0 to 3)< ="1111"; -- start of cmd
            DataOut(4 to 7)< ="0011"; -- cmd length
            visual_S0_current < = S11;
          elsif (a_comma = '1') then
            DataOut< ="00111100"; --0x3c
            visual_S0_current < = S3;
          else
            visual_S0_current < = S0;
          end if;
 
        when S2 =>
          DataOut< =C_BACKPOFF; -- backpressure off
          visual_S0_current < = S9;
 
        when S17 =>
          if (bp_stop = '0') then
            DataOut< =(others =>'0');
            ack< ='0';
            a_ack< ='0';
            bp_ack< ='0';
            visual_S0_current < = S0;
          else
            visual_S0_current < = S17;
          end if;
 
        when S9 =>
          DataOut< =(others =>'0');
          bp_ack< ='1';
          visual_S0_current < = S17;
 
        when S10 =>
          DataOut< =C_BACKPON; -- backpressure on
          visual_S0_current < = S16;
 
        when S16 =>
          DataOut< =(others =>'0');
          bp_ack< ='1';
          visual_S0_current < = S19;
 
        when S19 =>
          if (bp_start = '0') then
            DataOut< =(others =>'0');
            ack< ='0';
            a_ack< ='0';
            bp_ack< ='0';
            visual_S0_current < = S0;
          else
            visual_S0_current < = S19;
          end if;
 
        when S3 =>
          DataOut< =(others=>'0');
          a_ack< ='1';
          visual_S0_current < = S4;
 
        when S4 =>
          if (a_comma = '0') then
            DataOut< =(others =>'0');
            ack< ='0';
            a_ack< ='0';
            bp_ack< ='0';
            visual_S0_current < = S0;
          else
            visual_S0_current < = S4;
          end if;
 
        when S11 =>
          DataOut< =C_IDLE; -- send idle = comma
          visual_S0_current < = S12;
 
        when S12 =>
          DataOut< = ts_16(7 downto 0);
          visual_S0_current < = S13;
 
        when S13 =>
          DataOut< =ts_16(15 downto 8);
          visual_S0_current < = S14;
 
        when S14 =>
          DataOut< =(others =>'0');
          a_ack< ='1';
          visual_S0_current < = S15;
 
        when S15 =>
          if (a_idle = '0') then
            DataOut< =(others =>'0');
            ack< ='0';
            a_ack< ='0';
            bp_ack< ='0';
            visual_S0_current < = S0;
          else
            visual_S0_current < = S15;
          end if;
 
        when S1 =>
          DataOut< =C_TRGREQ; -- TRIGGER REQUEST
          visual_S0_current < = S5;
 
        when S5 =>
          DataOut< = tag(7 downto 0);
          visual_S0_current < = S6;
 
        when S6 =>
          DataOut< =tag(15 downto 8);
          visual_S0_current < = S8;
 
        when S7 =>
          if (strobe = '0') then
            DataOut< =(others =>'0');
            ack< ='0';
            a_ack< ='0';
            bp_ack< ='0';
            visual_S0_current < = S0;
          else
            visual_S0_current < = S7;
          end if;
 
        when S8 =>
          DataOut< =(others =>'0');
          ack< ='1';
          visual_S0_current < = S7;
 
        when others =>
 
          DataOut< =(others =>'0');
          ack< ='0';
          a_ack< ='0';
          bp_ack< ='0';
          visual_S0_current < = S0;
      end case;
    end if;
  end process ctrl_S0;
 
end ctrl;
----------------------------------------------------
--  
--  Library Name :  GTS
--  Unit    Name :  trg_req_gen
--  Unit    Type :  State Machine
--  
------------------------------------------------------
 
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.STD_LOGIC_SIGNED.all;
use ieee.NUMERIC_STD.all;
library synplify;
use synplify.attributes.all;
 
 
entity trg_req_gen is
  port (
        bclk : in std_logic;
        lreset : in std_logic;
        l_trg : in std_logic_vector(1 downto 0 );
        l_tag : in std_logic_vector(7 downto 0 );
        tag : out std_logic_vector(15 downto 0 );
        strobe : out std_logic;
        ack : in std_logic;
        clear_idle : out std_logic
        );
 
end trg_req_gen;
 
 
architecture trg_req_gen of trg_req_gen is
 
  type visual_S0_states is (S0, S1, S2, S3, S5, S6, S7, S8, S9);
  signal visual_S0_current : visual_S0_states;
 
 
begin
 
 
 
  -- Synchronous process
  trg_req_gen_S0:
  process (bclk)
  begin
 
    if (bclk'event and bclk = '1') then
      if (lreset = '1') then
        strobe < ='0';
        tag< =(others => '0');
        visual_S0_current < = S0;
      else
 
        case visual_S0_current is
          when S0 =>
            if (l_trg(0) = '1') then
              clear_idle< ='1';
              visual_S0_current < = S5;
            else
              visual_S0_current < = S0;
            end if;
 
          when S1 =>
            tag(7 downto 0) < = l_tag;
            visual_S0_current < = S2;
 
          when S2 =>
            strobe < = '1';
            visual_S0_current < = S3;
 
          when S3 =>
            if (ack = '1') then
              strobe < ='0';
              tag< =(others => '0');
              visual_S0_current < = S0;
            else
              visual_S0_current < = S3;
            end if;
 
          when S5 =>
            visual_S0_current < = S6;
 
          when S6 =>
            clear_idle< ='0';
            visual_S0_current < = S7;
 
          when S7 =>
            visual_S0_current < = S9;
 
          when S8 =>
            tag(15 downto 8) < = l_tag;
            visual_S0_current < = S1;
 
          when S9 =>
            visual_S0_current < = S8;
 
          when others =>
 
            strobe < ='0';
            tag< =(others => '0');
            visual_S0_current < = S0;
        end case;
      end if;
    end if;
  end process trg_req_gen_S0;
 
end trg_req_gen;
----------------------------------------------------
--  
--  Library Name :  GTS
--  Unit    Name :  cmd_enc
--  Unit    Type :  Block Diagram
--  
------------------------------------------------------
 
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.STD_LOGIC_SIGNED.all;
use ieee.NUMERIC_STD.all;
library synplify;
use synplify.attributes.all;
 
 
entity cmd_enc is
  port (
        DoubleErr : out std_ulogic;
        l_tag : in std_logic_vector(7 downto 0 );
        TXDATA : out std_logic_vector(15 downto 0 );
        MultipleErr : out std_ulogic;
        msg_in : in std_logic_vector(7 downto 0 );
        SingleErr : out std_ulogic;
        bclk : in std_logic;
        msg_strobe : in std_logic_vector(1 downto 0 );
        lreset : in std_logic;
        backpressure : in std_logic;
        l_trg : in std_logic_vector(1 downto 0 );
        DataCorr : out std_logic_vector(0 to 7 );
        a_comma : in std_logic;
        clear_idle : out std_logic;
        a_ack : out std_logic;
        a_idle : in std_logic;
        ts_16 : in std_logic_vector(15 downto 0 )
        );
 
 
end cmd_enc;
 
 
use work.all;
architecture cmd_enc of cmd_enc is
 
  signal bp_start : std_logic;
  signal bp_ack : std_logic;
  signal bp_stop : std_logic;
  signal DataOut : std_logic_vector(0 to 7 );
  signal g : std_logic_vector(0 to 7 );
  signal strobe : std_logic;
  signal tag : std_logic_vector(15 downto 0 );
  signal ack : std_logic;
  signal CheckOut : std_logic_vector(0 to 7 );
  component trg_req_gen
      port (
            bclk : in std_logic;
            lreset : in std_logic;
            l_trg : in std_logic_vector(1 downto 0 );
            l_tag : in std_logic_vector(7 downto 0 );
            tag : out std_logic_vector(15 downto 0 );
            strobe : out std_logic;
            ack : in std_logic;
            clear_idle : out std_logic
            );
  end component;
  component ctrl
      port (
            msg_in : in std_logic_vector(7 downto 0 );
            msg_strobe : in std_logic_vector(1 downto 0 );
            bclk : in std_logic;
            lreset : in std_logic;
            tag : in std_logic_vector(15 downto 0 );
            strobe : in std_logic;
            ack : out std_logic;
            DataOut : out std_logic_vector(0 to 7 );
            ts_16 : in std_logic_vector(15 downto 0 );
            a_idle : in std_logic;
            a_comma : in std_logic;
            a_ack : out std_logic;
            bp_ack : out std_logic;
            bp_stop : in std_logic;
            bp_start : in std_logic
            );
  end component;
  component Hamming8
      port (
            DataOut : in std_logic_vector(0 to 7 );
            CheckOut : out std_logic_vector(0 to 7 );
            DataIn : in std_logic_vector(0 to 7 );
            CheckIn : in std_logic_vector(0 to 7 );
            DataCorr : out std_logic_vector(0 to 7 );
            SingleErr : out std_ulogic;
            DoubleErr : out std_ulogic;
            MultipleErr : out std_ulogic
            );
  end component;
  component backp_ctrl
      port (
            backpressure : in std_logic;
            bclk : in std_logic;
            lreset : in std_logic;
            bp_start : out std_logic;
            bp_stop : out std_logic;
            bp_ack : in std_logic
            );
  end component;
 
  -- Start Configuration Specification
  -- ++ for all : trg_req_gen use entity work.trg_req_gen(trg_req_gen);
  -- ++ for all : ctrl use entity work.ctrl(ctrl);
  -- ++ for all : Hamming8 use entity work.Hamming8(RTL);
  -- ++ for all : backp_ctrl use entity work.backp_ctrl(backp_ctrl);
  -- End Configuration Specification
 
begin
 
  inst_trg_req_gen: trg_req_gen
    port map (
              bclk => bclk,
              lreset => lreset,
              l_trg => l_trg(1 downto 0),
              l_tag => l_tag(7 downto 0),
              tag => tag(15 downto 0),
              strobe => strobe,
              ack => ack,
              clear_idle => clear_idle
              );
 
  cmd_enc_ctrl: ctrl
    port map (
              msg_in => msg_in(7 downto 0),
              msg_strobe => msg_strobe(1 downto 0),
              bclk => bclk,
              lreset => lreset,
              tag => tag(15 downto 0),
              strobe => strobe,
              ack => ack,
              DataOut => DataOut(0 to 7),
              ts_16 => ts_16(15 downto 0),
              a_idle => a_idle,
              a_comma => a_comma,
              a_ack => a_ack,
              bp_ack => bp_ack,
              bp_stop => bp_stop,
              bp_start => bp_start
              );
 
  inst_Hamming8: Hamming8
    port map (
              DataOut => DataOut(0 to 7),
              CheckOut => CheckOut(0 to 7),
              DataIn => g(0 to 7),
              CheckIn => g(0 to 7),
              DataCorr => DataCorr(0 to 7),
              SingleErr => SingleErr,
              DoubleErr => DoubleErr,
              MultipleErr => MultipleErr
              );
 
  inst_backp_ctrl: backp_ctrl
    port map (
              backpressure => backpressure,
              bclk => bclk,
              lreset => lreset,
              bp_start => bp_start,
              bp_stop => bp_stop,
              bp_ack => bp_ack
              );
 
  TXDATA(15 downto 8) < = DataOut(0 to 7);
  TXDATA(7 downto 0) < = CheckOut(0 to 7);
 
      g(0 to 7) < = (others => '0');
end cmd_enc;
----------------------------------------------------
--  
--  Library Name :  GTS
--  Unit    Name :  MGT_custom
--  Unit    Type :  Text Unit
--  
------------------------------------------------------
-- Module MGT_custom
-- Generated by Xilinx Architecture Wizard
-- VHDL
-- Written for synthesis tool: Synplicity
-- Xilinx Device: XC2VP7-FF672-6

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.all;
-- synopsys translate_on

entity MGT_custom is
    port (
        CONFIGENABLE : in std_logic;
        CONFIGIN : in std_logic;
        ENMCOMMAALIGN : in std_logic;
        ENPCOMMAALIGN : in std_logic;
        ENCHANSYNC : in std_logic;
        LOOPBACK : in std_logic_vector (1 downto 0);
        POWERDOWN : in std_logic;
        REFCLK : in std_logic;
        REFCLK2 : in std_logic;
        REFCLKSEL : in std_logic;
        BREFCLK : in std_logic;
        BREFCLK2 : in std_logic;
        RXN : in std_logic;
        RXP : in std_logic;
        RXPOLARITY : in std_logic;
        RXRESET : in std_logic;
        RXUSRCLK : in std_logic;
        RXUSRCLK2 : in std_logic;
        TXBYPASS8B10B : in std_logic_vector (1 downto 0);
        TXCHARDISPMODE : in std_logic_vector (1 downto 0);
        TXCHARDISPVAL : in std_logic_vector (1 downto 0);
        TXCHARISK : in std_logic_vector (1 downto 0);
        TXDATA : in std_logic_vector (15 downto 0);
        TXFORCECRCERR : in std_logic;
        TXINHIBIT : in std_logic;
        TXPOLARITY : in std_logic;
        TXRESET : in std_logic;
        TXUSRCLK : in std_logic;
        TXUSRCLK2 : in std_logic;
        CHBONDDONE : out std_logic;
        CONFIGOUT : out std_logic;
        RXBUFSTATUS : out std_logic_vector (1 downto 0);
        RXCHARISCOMMA : out std_logic_vector (1 downto 0);
        RXCHARISK : out std_logic_vector (1 downto 0);
        RXCHECKINGCRC : out std_logic;
        RXCLKCORCNT : out std_logic_vector (2 downto 0);
        RXCOMMADET : out std_logic;
        RXCRCERR : out std_logic;
        RXDATA : out std_logic_vector (15 downto 0);
        RXDISPERR : out std_logic_vector (1 downto 0);
        RXLOSSOFSYNC : out std_logic_vector (1 downto 0);
        RXNOTINTABLE : out std_logic_vector (1 downto 0);
        RXREALIGN : out std_logic;
        RXRECCLK : out std_logic;
        RXRUNDISP : out std_logic_vector (1 downto 0);
        TXBUFERR : out std_logic;
        TXKERR : out std_logic_vector (1 downto 0);
        TXN : out std_logic;
        TXP : out std_logic;
        TXRUNDISP : out std_logic_vector (1 downto 0));
end MGT_custom;



architecture STRUCT of MGT_custom is
   signal GND : std_logic_vector (3 downto 0);
   signal GND1 : std_logic_vector (31 downto 0);
   signal RXCHARISCOMMA_float : std_logic_vector (1 downto 0);
   signal RXCHARISK_float : std_logic_vector (1 downto 0);
   signal RXDATA_float : std_logic_vector (15 downto 0);
   signal RXDISPERR_float : std_logic_vector (1 downto 0);
   signal RXNOTINTABLE_float : std_logic_vector (1 downto 0);
   signal RXRUNDISP_float : std_logic_vector (1 downto 0);
   signal TXKERR_float : std_logic_vector (1 downto 0);
   signal TXRUNDISP_float : std_logic_vector (1 downto 0);


   component GT_CUSTOM
    generic( 
       ALIGN_COMMA_MSB : boolean := FALSE;
       CHAN_BOND_LIMIT : integer := 16;
       CHAN_BOND_MODE : string := "OFF";
       CHAN_BOND_OFFSET : integer := 8;
       CHAN_BOND_ONE_SHOT : boolean := FALSE;
       CHAN_BOND_SEQ_1_1 : bit_vector := "00000000000";
       CHAN_BOND_SEQ_1_2 : bit_vector := "00000000000";
       CHAN_BOND_SEQ_1_3 : bit_vector := "00000000000";
       CHAN_BOND_SEQ_1_4 : bit_vector := "00000000000";
       CHAN_BOND_SEQ_2_1 : bit_vector := "00000000000";
       CHAN_BOND_SEQ_2_2 : bit_vector := "00000000000";
       CHAN_BOND_SEQ_2_3 : bit_vector := "00000000000";
       CHAN_BOND_SEQ_2_4 : bit_vector := "00000000000";
       CHAN_BOND_SEQ_2_USE : boolean := FALSE;
       CHAN_BOND_SEQ_LEN : integer := 1;
       CHAN_BOND_WAIT : integer := 8;
       CLK_COR_INSERT_IDLE_FLAG : boolean := FALSE;
       CLK_COR_KEEP_IDLE : boolean := FALSE;
       CLK_COR_REPEAT_WAIT : integer := 1;
       CLK_COR_SEQ_1_1 : bit_vector := "00000000000";
       CLK_COR_SEQ_1_2 : bit_vector := "00000000000";
       CLK_COR_SEQ_1_3 : bit_vector := "00000000000";
       CLK_COR_SEQ_1_4 : bit_vector := "00000000000";
       CLK_COR_SEQ_2_1 : bit_vector := "00000000000";
       CLK_COR_SEQ_2_2 : bit_vector := "00000000000";
       CLK_COR_SEQ_2_3 : bit_vector := "00000000000";
       CLK_COR_SEQ_2_4 : bit_vector := "00000000000";
       CLK_COR_SEQ_2_USE : boolean := FALSE;
       CLK_COR_SEQ_LEN : integer := 1;
       CLK_CORRECT_USE : boolean := TRUE;
       COMMA_10B_MASK : bit_vector := "1111111000";
       CRC_END_OF_PKT : string := "K29_7";
       CRC_FORMAT : string := "USER_MODE";
       CRC_START_OF_PKT : string := "K27_7";
       DEC_MCOMMA_DETECT : boolean := TRUE;
       DEC_PCOMMA_DETECT : boolean := TRUE;
       DEC_VALID_COMMA_ONLY : boolean := TRUE;
       MCOMMA_10B_VALUE : bit_vector := "1100000000";
       MCOMMA_DETECT : boolean := TRUE;
       PCOMMA_10B_VALUE : bit_vector := "0011111000";
       PCOMMA_DETECT : boolean := TRUE;
       REF_CLK_V_SEL : integer := 1;		--- < < < < ----
       RX_BUFFER_USE : boolean := TRUE;
       RX_CRC_USE : boolean := FALSE;
       RX_DATA_WIDTH : integer := 2;
       RX_DECODE_USE : boolean := TRUE;
       RX_LOS_INVALID_INCR : integer := 1;
       RX_LOS_THRESHOLD : integer := 4;
       RX_LOSS_OF_SYNC_FSM : boolean := TRUE;
       SERDES_10B : boolean := FALSE;
       TERMINATION_IMP : integer := 50;
       TX_BUFFER_USE : boolean := TRUE;
       TX_CRC_FORCE_VALUE : bit_vector := "11010110";
       TX_CRC_USE : boolean := FALSE;
       TX_DATA_WIDTH : integer := 2;
       TX_DIFF_CTRL : integer := 500;
       TX_PREEMPHASIS : integer := 0
     );
     port (
       CHBONDI : in std_logic_vector (3 downto 0);
       CONFIGENABLE : in std_logic;
       CONFIGIN : in std_logic;
       ENMCOMMAALIGN : in std_logic;
       ENPCOMMAALIGN : in std_logic;
       ENCHANSYNC : in std_logic;
       LOOPBACK : in std_logic_vector (1 downto 0);
       POWERDOWN : in std_logic;
       REFCLK : in std_logic;
       REFCLK2 : in std_logic;
       REFCLKSEL : in std_logic;
       BREFCLK : in std_logic;
       BREFCLK2 : in std_logic;
       RXN : in std_logic;
       RXP : in std_logic;
       RXPOLARITY : in std_logic;
       RXRESET : in std_logic;
       RXUSRCLK : in std_logic;
       RXUSRCLK2 : in std_logic;
       TXBYPASS8B10B : in std_logic_vector (3 downto 0);
       TXCHARDISPMODE : in std_logic_vector (3 downto 0);
       TXCHARDISPVAL : in std_logic_vector (3 downto 0);
       TXCHARISK : in std_logic_vector (3 downto 0);
       TXDATA : in std_logic_vector (31 downto 0);
       TXFORCECRCERR : in std_logic;
       TXINHIBIT : in std_logic;
       TXPOLARITY : in std_logic;
       TXRESET : in std_logic;
       TXUSRCLK : in std_logic;
       TXUSRCLK2 : in std_logic;
       CHBONDDONE : out std_logic;
       CHBONDO : out std_logic_vector (3 downto 0);
       CONFIGOUT : out std_logic;
       RXBUFSTATUS : out std_logic_vector (1 downto 0);
       RXCHARISCOMMA : out std_logic_vector (3 downto 0);
       RXCHARISK : out std_logic_vector (3 downto 0);
       RXCHECKINGCRC : out std_logic;
       RXCLKCORCNT : out std_logic_vector (2 downto 0);
       RXCOMMADET : out std_logic;
       RXCRCERR : out std_logic;
       RXDATA : out std_logic_vector (31 downto 0);
       RXDISPERR : out std_logic_vector (3 downto 0);
       RXLOSSOFSYNC : out std_logic_vector (1 downto 0);
       RXNOTINTABLE : out std_logic_vector (3 downto 0);
       RXREALIGN : out std_logic;
       RXRECCLK : out std_logic;
       RXRUNDISP : out std_logic_vector (3 downto 0);
       TXBUFERR : out std_logic;
       TXKERR : out std_logic_vector (3 downto 0);
       TXN : out std_logic;
       TXP : out std_logic;
       TXRUNDISP : out std_logic_vector (3 downto 0)
       );
   end component;

begin
   GT_CUSTOM_INST : GT_CUSTOM
    Generic map (
      ALIGN_COMMA_MSB => TRUE,
      CHAN_BOND_LIMIT => 16,
      CHAN_BOND_MODE => "OFF",
      CHAN_BOND_OFFSET => 8,
      CHAN_BOND_ONE_SHOT => FALSE,
      CHAN_BOND_SEQ_1_1 => "00000000000",
      CHAN_BOND_SEQ_1_2 => "00000000000",
      CHAN_BOND_SEQ_1_3 => "00000000000",
      CHAN_BOND_SEQ_1_4 => "00000000000",
      CHAN_BOND_SEQ_2_1 => "00000000000",
      CHAN_BOND_SEQ_2_2 => "00000000000",
      CHAN_BOND_SEQ_2_3 => "00000000000",
      CHAN_BOND_SEQ_2_4 => "00000000000",
      CHAN_BOND_SEQ_2_USE => FALSE,
      CHAN_BOND_SEQ_LEN => 1,
      CHAN_BOND_WAIT => 8,
      CLK_CORRECT_USE => FALSE,
      CLK_COR_INSERT_IDLE_FLAG => FALSE,
      CLK_COR_KEEP_IDLE => FALSE,
      CLK_COR_REPEAT_WAIT => 1,
      CLK_COR_SEQ_1_1 => "00000000000",
      CLK_COR_SEQ_1_2 => "00000000000",
      CLK_COR_SEQ_1_3 => "00000000000",
      CLK_COR_SEQ_1_4 => "00000000000",
      CLK_COR_SEQ_2_1 => "00000000000",
      CLK_COR_SEQ_2_2 => "00000000000",
      CLK_COR_SEQ_2_3 => "00000000000",
      CLK_COR_SEQ_2_4 => "00000000000",
      CLK_COR_SEQ_2_USE => FALSE,
      CLK_COR_SEQ_LEN => 1,
      COMMA_10B_MASK => "1111111000",
      CRC_END_OF_PKT => "K29_7",
      CRC_FORMAT => "USER_MODE",
      CRC_START_OF_PKT => "K27_7",
      DEC_MCOMMA_DETECT => TRUE,
      DEC_PCOMMA_DETECT => TRUE,
      DEC_VALID_COMMA_ONLY => TRUE,
      MCOMMA_10B_VALUE => "1100000000",
      MCOMMA_DETECT => TRUE,
      PCOMMA_10B_VALUE => "0011111000",
      PCOMMA_DETECT => TRUE,
      RX_BUFFER_USE => TRUE,
      RX_CRC_USE => FALSE,
      RX_DATA_WIDTH => 2,
      RX_DECODE_USE => TRUE,
      RX_LOSS_OF_SYNC_FSM => TRUE,
      RX_LOS_INVALID_INCR => 1,
      RX_LOS_THRESHOLD => 4,
      TERMINATION_IMP => 50,
      SERDES_10B => FALSE,
      TX_BUFFER_USE => TRUE,
      TX_CRC_FORCE_VALUE => "11010110",
      TX_CRC_USE => FALSE,
      TX_DATA_WIDTH => 2,
      TX_DIFF_CTRL => 500,
      TX_PREEMPHASIS => 0,
      REF_CLK_V_SEL => 0)
     port map (
      CHBONDI(3 downto 0) => GND(3 downto 0),
      CONFIGENABLE => CONFIGENABLE,
      CONFIGIN => CONFIGIN,
      ENMCOMMAALIGN => ENMCOMMAALIGN,
      ENPCOMMAALIGN => ENPCOMMAALIGN,
      ENCHANSYNC => ENCHANSYNC,
      LOOPBACK(1 downto 0) => LOOPBACK(1 downto 0),
      POWERDOWN => POWERDOWN,
      REFCLK => REFCLK,
      REFCLK2 => REFCLK2,
      REFCLKSEL => REFCLKSEL,
      BREFCLK => BREFCLK,
      BREFCLK2 => BREFCLK2,
      RXN => RXN,
      RXP => RXP,
      RXPOLARITY => RXPOLARITY,
      RXRESET => RXRESET,
      RXUSRCLK => RXUSRCLK,
      RXUSRCLK2 => RXUSRCLK2,
      TXBYPASS8B10B(1 downto 0) => TXBYPASS8B10B(1 downto 0),
      TXBYPASS8B10B(3 downto 2) => GND(1 downto 0),
      TXCHARDISPMODE(1 downto 0) => TXCHARDISPMODE(1 downto 0),
      TXCHARDISPMODE(3 downto 2) => GND(1 downto 0),
      TXCHARDISPVAL(1 downto 0) => TXCHARDISPVAL(1 downto 0),
      TXCHARDISPVAL(3 downto 2) => GND(1 downto 0),
      TXCHARISK(1 downto 0) => TXCHARISK(1 downto 0),
      TXCHARISK(3 downto 2) => GND(1 downto 0),
      TXDATA(15 downto 0) => TXDATA(15 downto 0),
      TXDATA(31 downto 16) => GND1(15 downto 0),
      TXFORCECRCERR => TXFORCECRCERR,
      TXINHIBIT => TXINHIBIT,
      TXPOLARITY => TXPOLARITY,
      TXRESET => TXRESET,
      TXUSRCLK => TXUSRCLK,
      TXUSRCLK2 => TXUSRCLK2,
      CHBONDDONE => CHBONDDONE,
      CONFIGOUT => CONFIGOUT,
      RXBUFSTATUS(1 downto 0) => RXBUFSTATUS(1 downto 0),
      RXCHARISCOMMA(1 downto 0) => RXCHARISCOMMA(1 downto 0),
      RXCHARISCOMMA(3 downto 2) => RXCHARISCOMMA_float(1 downto 0),
      RXCHARISK(1 downto 0) => RXCHARISK(1 downto 0),
      RXCHARISK(3 downto 2) => RXCHARISK_float(1 downto 0),
      RXCHECKINGCRC => RXCHECKINGCRC,
      RXCLKCORCNT(2 downto 0) => RXCLKCORCNT(2 downto 0),
      RXCOMMADET => RXCOMMADET,
      RXCRCERR => RXCRCERR,
      RXDATA(15 downto 0) => RXDATA(15 downto 0),
      RXDATA(31 downto 16) => RXDATA_float(15 downto 0),
      RXDISPERR(1 downto 0) => RXDISPERR(1 downto 0),
      RXDISPERR(3 downto 2) => RXDISPERR_float(1 downto 0),
      RXLOSSOFSYNC(1 downto 0) => RXLOSSOFSYNC(1 downto 0),
      RXNOTINTABLE(1 downto 0) => RXNOTINTABLE(1 downto 0),
      RXNOTINTABLE(3 downto 2) => RXNOTINTABLE_float(1 downto 0),
      RXREALIGN => RXREALIGN,
      RXRECCLK => RXRECCLK,
      RXRUNDISP(1 downto 0) => RXRUNDISP(1 downto 0),
      RXRUNDISP(3 downto 2) => RXRUNDISP_float(1 downto 0),
      TXBUFERR => TXBUFERR,
      TXKERR(1 downto 0) => TXKERR(1 downto 0),
      TXKERR(3 downto 2) => TXKERR_float(1 downto 0),
      TXN => TXN,
      TXP => TXP,
      TXRUNDISP(1 downto 0) => TXRUNDISP(1 downto 0),
      TXRUNDISP(3 downto 2) => TXRUNDISP_float(1 downto 0));

   GND < = "0000";
   GND1 < = "00000000000000000000000000000000";
end STRUCT;



----------------------------------------------------
--  
--  Library Name :  GTS
--  Unit    Name :  Hamming4
--  Unit    Type :  Text Unit
--  
------------------------------------------------------


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
-- use work.EDAC.all;

entity Hamming4 is
   port(
      DataOut:       in    std_logic_vector(0 to 3);    -- Output data bits
      CheckOut:      out   std_logic_vector(0 to 3);    -- Output check bits

      DataIn:        in    std_logic_vector(0 to 3);    -- Input data bits
      CheckIn:       in    std_logic_vector(0 to 3);    -- Input check bits

      DataCorr:      out   std_logic_vector(0 to 3);    -- Corrected data bits
      SingleErr:     out   Std_ULogic;          -- Single error
      DoubleErr:     out   Std_ULogic;          -- Double error
      MultipleErr:   out   Std_ULogic          -- Uncorrectable error
   );
end Hamming4;



architecture RTL of Hamming4 is

 begin

   process (DataOut,DataIn,CheckIn)
      variable PgenL:         Std_Logic_Vector(0 to 3);  -- Generated parity
      variable SyndL:         Std_Logic_Vector(0 to 3);  -- Syndrome
      variable FlipL:         Std_Logic_Vector(0 to 3);  -- Bits to invert
      variable ChipL:         Std_Logic_Vector(0 to 3);  -- Errors in parity

     begin

      -- Check bit generator
      PgenL(0) := not (DataIn(0) xor DataIn(1) xor DataIn(2));
      PgenL(1) :=      DataIn(0) xor DataIn(1) xor DataIn(3);
      PgenL(2) := not (DataIn(0) xor DataIn(2) xor DataIn(3));
      PgenL(3) :=      DataIn(1) xor DataIn(2) xor DataIn(3);

      -- Syndrome bit generator
      SyndL(0) := PgenL(0) xor not CheckIn(0);
      SyndL(1) := PgenL(1) xor not CheckIn(1);
      SyndL(2) := PgenL(2) xor     CheckIn(2);
      SyndL(3) := PgenL(3) xor     CheckIn(3);

      -- Bit corrector
      if SyndL="1110" then
         FlipL(0) := '1';
      else
         FlipL(0) := '0';
      end if;
      if SyndL="1101" then
         FlipL(1) := '1';
      else
         FlipL(1) := '0';
      end if;
      if SyndL="1011" then
         FlipL(2) := '1';
      else
         FlipL(2) := '0';
      end if;
      if SyndL="0111" then
         FlipL(3) := '1';
      else
         FlipL(3) := '0';
      end if;

      -- Single error in check bits
      if SyndL="0001" then
         ChipL(0) := '1';
      else
         ChipL(0) := '0';
      end if;
      if SyndL="0010" then
         ChipL(1) := '1';
      else
         ChipL(1) := '0';
      end if;
      if SyndL="0100" then
         ChipL(2) := '1';
      else
         ChipL(2) := '0';
      end if;
      if SyndL="1000" then
         ChipL(3) := '1';
      else
         ChipL(3) := '0';
      end if;

      -- Corrected data
      DataCorr(0) < = DataIn(0) xor FlipL(0);
      DataCorr(1) < = DataIn(1) xor FlipL(1);
      DataCorr(2) < = DataIn(2) xor FlipL(2);
      DataCorr(3) < = DataIn(3) xor FlipL(3);

      -- Check bits
      CheckOut(0) < = not (not (DataOut(0) xor DataOut(1) xor DataOut(2)));
      CheckOut(1) < = not (     DataOut(0) xor DataOut(1) xor DataOut(3));
      CheckOut(2) < =     (not (DataOut(0) xor DataOut(2) xor DataOut(3)));
      CheckOut(3) < =     (     DataOut(1) xor DataOut(2) xor DataOut(3));

      -- Single correctable error flag
      SingleErr   < = (FlipL(0) or FlipL(1) or FlipL(2) or FlipL(3)) xor
                     (ChipL(0) or ChipL(1) or ChipL(2) or ChipL(3));

      -- double correctable error flag
      DoubleErr   < = '0';

      -- Uncorrectable error flag
      if SyndL="0011" or SyndL="0101" or
         SyndL="0110" or SyndL="1001" or
         SyndL="1010" or SyndL="1100" or
         SyndL="1111" then
         MultipleErr    < = '1';
      else
         MultipleErr    < = '0';
      end if;
   end process;
 end RTL;



----------------------------------------------------
--  
--  Library Name :  GTS
--  Unit    Name :  cmd_dec_ctrl
--  Unit    Type :  State Machine
--  
------------------------------------------------------
 
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.STD_LOGIC_SIGNED.all;
use ieee.NUMERIC_STD.all;
library GTS;
use GTS.gts_pack.all;
library synplify;
use synplify.attributes.all;
 
 
entity cmd_dec_ctrl is
  port (
        L1A : out std_logic_vector(15 downto 0 );
        reset : out std_logic;
        event_num : out std_logic_vector(23 downto 0 );
        bcast_strobe : out std_logic;
        bcast_out : out std_logic_vector(7 downto 0 );
        L1A_arrived : out std_logic;
        bclk : in std_logic;
        lreset : in std_logic;
        nib : in std_logic_vector(0 to 3 );
        outofsync : in std_logic;
        refclksel : out std_logic
        );
 
end cmd_dec_ctrl;
 
 
architecture cmd_dec_ctrl of cmd_dec_ctrl is
 
  signal index : unsigned(3 downto 0 );
  signal nib_count : unsigned(3 downto 0 );
  signal payload : std_logic_vector(63 downto 0 );
 
  type visual_S11_states is (S11, S0, S1, S2, S9, S3, S4, S5, S6, S8);
  signal visual_S11_current : visual_S11_states;
 
 
begin
 
 
 
  -- Synchronous process
  cmd_dec_ctrl_S11:
  process (bclk, lreset)
  begin
 
    if (lreset = '1') then
      refclksel< ='0';
      visual_S11_current < = S11;
    elsif (bclk'event and bclk = '1') then
 
      case visual_S11_current is
        when S11 =>
          index < ="0000";
          L1A_arrived< ='0';
          reset< ='0';
          visual_S11_current < = S0;
 
        when S0 =>
          if (nib = "1111" and outofsync = '0') then  --  start of frame
            visual_S11_current < = S9;
          else
            visual_S11_current < = S0;
          end if;
 
        when S1 =>
          index< =index+1;
          case index is
            when "0000" => payload(3 downto 0) < = nib;
            when "0001" => payload(7 downto 4) < =nib;
            when "0010" => payload(11 downto 8)< =nib;
            when "0011" => payload(15 downto 12) < = nib;
            when "0100" => payload(19 downto 16) < =nib;
            when "0101" => payload(23 downto 20)< =nib;
            when "0110" => payload(27 downto 24) < = nib;
            when "0111" => payload(31 downto 28) < =nib;
            when "1000" => payload(35 downto 32)< =nib;
            when "1001" => payload(39 downto 36) < = nib;
            when "1010" => payload(43 downto 40) < =nib;
            when "1011" => payload(47 downto 44)< =nib;
            when "1100" => payload(51 downto 48) < = nib;
            when "1101" => payload(55 downto 52) < =nib;
            when "1110" => payload(59 downto 56)< =nib;
            when "1111" => payload(63 downto 60)< =nib;
            when others => payload< =(others =>'0');
          end case;
          visual_S11_current < = S2;
 
        when S2 =>
          if (index = nib_count) then
            visual_S11_current < = S3;
          else
            index< =index+1;
            case index is
              when "0000" => payload(3 downto 0) < = nib;
              when "0001" => payload(7 downto 4) < =nib;
              when "0010" => payload(11 downto 8)< =nib;
              when "0011" => payload(15 downto 12) < = nib;
              when "0100" => payload(19 downto 16) < =nib;
              when "0101" => payload(23 downto 20)< =nib;
              when "0110" => payload(27 downto 24) < = nib;
              when "0111" => payload(31 downto 28) < =nib;
              when "1000" => payload(35 downto 32)< =nib;
              when "1001" => payload(39 downto 36) < = nib;
              when "1010" => payload(43 downto 40) < =nib;
              when "1011" => payload(47 downto 44)< =nib;
              when "1100" => payload(51 downto 48) < = nib;
              when "1101" => payload(55 downto 52) < =nib;
              when "1110" => payload(59 downto 56)< =nib;
              when "1111" => payload(63 downto 60)< =nib;
              when others => payload< =(others =>'0');
            end case;
            visual_S11_current < = S2;
          end if;
 
        when S9 =>
          nib_count < = unsigned (nib);
          visual_S11_current < = S1;
 
        when S3 =>
          if (payload(3 downto 0) = C_L1A) then
            L1A< = payload(19 downto 4);
            event_num< = payload(43 downto 20);
            L1A_arrived< ='1';
            visual_S11_current < = S4;
          elsif (payload(3 downto 0) = C_SRESET) then
            reset< ='1';
            bcast_strobe< ='1';
            bcast_out(3 downto 0)< = C_SRESET;
            bcast_out(7 downto 4)< ="0000";
            visual_S11_current < = S6;
          else
            index < ="0000";
            L1A_arrived< ='0';
            reset< ='0';
            visual_S11_current < = S0;
          end if;
 
        when S4 =>
          visual_S11_current < = S5;
 
        when S5 =>
          index < ="0000";
          L1A_arrived< ='0';
          reset< ='0';
          visual_S11_current < = S0;
 
        when S6 =>
          refclksel< ='0';
          bcast_strobe< ='0';
          visual_S11_current < = S8;
 
        when S8 =>
          index < ="0000";
          L1A_arrived< ='0';
          reset< ='0';
          visual_S11_current < = S0;
 
        when others =>
 
          refclksel< ='0';
          visual_S11_current < = S11;
      end case;
    end if;
  end process cmd_dec_ctrl_S11;
 
end cmd_dec_ctrl;
----------------------------------------------------
--  
--  Library Name :  GTS
--  Unit    Name :  cmd_dec
--  Unit    Type :  Block Diagram
--  
------------------------------------------------------
 
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.STD_LOGIC_SIGNED.all;
use ieee.NUMERIC_STD.all;
library GTS;
use GTS.gts_pack.all;
library synplify;
use synplify.attributes.all;
 
 
entity cmd_dec is
  port (
        refclksel : out std_logic;
        bcast_out : out std_logic_vector(7 downto 0 );
        DoubleErr : out std_ulogic;
        event_num : out std_logic_vector(23 downto 0 );
        MultipleErr : out std_ulogic;
        SingleErr : out std_ulogic;
        outofsync : in std_logic;
        bclk : in std_logic;
        L1A : out std_logic_vector(15 downto 0 );
        msb : in std_logic_vector(7 downto 0 );
        L1A_arrived : out std_logic;
        lreset : in std_logic;
        bcast_strobe : out std_logic;
        CheckOut : out std_logic_vector(0 to 3 );
        reset : out std_logic
        );
 
 
end cmd_dec;
 
 
use work.all;
architecture cmd_dec of cmd_dec is
 
  signal O : std_logic_vector(0 to 3 );
  signal nib : std_logic_vector(0 to 3 );
  signal DataIn : std_logic_vector(0 to 3 );
  signal CheckIn : std_logic_vector(0 to 3 );
  component cmd_dec_ctrl
      port (
            L1A : out std_logic_vector(15 downto 0 );
            reset : out std_logic;
            event_num : out std_logic_vector(23 downto 0 );
            bcast_strobe : out std_logic;
            bcast_out : out std_logic_vector(7 downto 0 );
            L1A_arrived : out std_logic;
            bclk : in std_logic;
            lreset : in std_logic;
            nib : in std_logic_vector(0 to 3 );
            outofsync : in std_logic;
            refclksel : out std_logic
            );
  end component;
  component Hamming4
      port (
            DataOut : in std_logic_vector(0 to 3 );
            CheckOut : out std_logic_vector(0 to 3 );
            DataIn : in std_logic_vector(0 to 3 );
            CheckIn : in std_logic_vector(0 to 3 );
            DataCorr : out std_logic_vector(0 to 3 );
            SingleErr : out std_ulogic;
            DoubleErr : out std_ulogic;
            MultipleErr : out std_ulogic
            );
  end component;
 
  -- Start Configuration Specification
  -- ++ for all : cmd_dec_ctrl use entity work.cmd_dec_ctrl(cmd_dec_ctrl);
  -- ++ for all : Hamming4 use entity work.Hamming4(RTL);
  -- End Configuration Specification
 
begin
 
  inst_cmd_dec_ctrl: cmd_dec_ctrl
    port map (
              L1A => L1A(15 downto 0),
              reset => reset,
              event_num => event_num(23 downto 0),
              bcast_strobe => bcast_strobe,
              bcast_out => bcast_out(7 downto 0),
              L1A_arrived => L1A_arrived,
              bclk => bclk,
              lreset => lreset,
              nib => nib(0 to 3),
              outofsync => outofsync,
              refclksel => refclksel
              );
 
  inst_Hamming4: Hamming4
    port map (
              DataOut => O(0 to 3),
              CheckOut => CheckOut(0 to 3),
              DataIn => DataIn(0 to 3),
              CheckIn => CheckIn(0 to 3),
              DataCorr => nib(0 to 3),
              SingleErr => SingleErr,
              DoubleErr => DoubleErr,
              MultipleErr => MultipleErr
              );
 
  DataIn(0 to 3) < = msb(3 downto 0);
  CheckIn(0 to 3) < = msb(7 downto 4);
 
      O(0 to 3) < = (others => '0');
end cmd_dec;
----------------------------------------------------
--  
--  Library Name :  GTS
--  Unit    Name :  t_decode
--  Unit    Type :  Text Unit
--  
------------------------------------------------------
------------------------------------------
------------------------------------------
-- Date        : Sun Mar 20 21:13:01 2005
--
-- Author      : 
--
-- Company     : 
--
-- Description : 
--
------------------------------------------
------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;


entity  t_decode  is
port (bclk : in std_logic ;
      lreset : in std_logic ;
      tstamp_err : out std_logic ;
      fiber_in : in std_logic_vector (15 downto 0);
      msk1 : in std_logic_vector (47 downto 0);
      msk2 : in std_logic_vector (47 downto 0);
      timestamp : out std_logic_vector (47 downto 0);     
      tstamp_lsw : out std_logic_vector (15 downto 0)
);
end;



------------------------------------------
------------------------------------------
-- Date        : Sun Mar 20 21:13:01 2005
--
-- Author      : 
--
-- Company     : 
--
-- Description : 
--
------------------------------------------
------------------------------------------
architecture  t_dec  of  t_decode  is

signal current, previous : std_logic_vector(47 downto 0);
begin

  process (bclk,lreset)
  
  variable evNumL,tmp : unsigned (47 downto 0);
  variable nib1,nib2 : std_logic_vector(3 downto 0);
   begin
     if lreset ='1' then
          current < = (others=>'0');
          previous < = (others=>'0');
     elsif (bclk'event and bclk='1') then
          evNumL := unsigned(current);
          nib1 := fiber_in(3 downto 0);
          nib2 := fiber_in(7 downto 4);
          if nib2(3)='1'  then
             evNumL := evNumL and unsigned(msk1);
             tmp := unsigned ("00000000000000000000000000000000000000000000" & (nib2 and "0111"));
             tmp := SHIFT_LEFT(tmp,to_integer(1+3*(unsigned(nib1))));
             evNumL := evNumL or tmp;
          else
             evNumL(3 downto 0) := unsigned(nib1);
             evNumL := evNumL and unsigned(msk2);
             tmp := unsigned ("00000000000000000000000000000000000000000000" & (nib2 and "0111"));
             tmp := SHIFT_LEFT(tmp,to_integer(1+3*(unsigned(nib1))));
             evNumL :=evNumL or tmp;
          end if;
          previous < = current;
          current < = std_logic_vector(evNumL);
          if unsigned(current) = (unsigned(previous)+1) then
            tstamp_err < ='0';
          else
            tstamp_err < ='1';
          end if;
          timestamp < = std_logic_vector(evNumL);
          tstamp_lsw < = std_logic_vector(evNumL(15 downto 0));
      end if;
    end process;
end t_dec;

----------------------------------------------------
--  
--  Library Name :  GTS
--  Unit    Name :  RTX
--  Unit    Type :  Block Diagram
--  
------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
 
 
entity RTX is
  port (
        tstamp_err : out std_logic;
        L1A : out std_logic_vector(15 downto 0 );
        lreset : in std_logic;
        timestamp : out std_logic_vector(47 downto 0 );
        RXBUFSTATUS : out std_logic_vector(1 downto 0 );
        bcast_out : out std_logic_vector(7 downto 0 );
        fiber_in_n : in std_logic;
        fiber_in_p : in std_logic;
        RXREALIGN : out std_logic;
        fiber_out_n : out std_logic;
        l_tag : in std_logic_vector(7 downto 0 );
        TXKERR : out std_logic_vector(1 downto 0 );
        fiber_out_p : out std_logic;
        gclk : out std_logic;
        CONFIGOUT : out std_logic;
        CHBONDDONE : out std_logic;
        L1A_fifo_full : in std_logic;
        event_num : out std_logic_vector(23 downto 0 );
        L1A_fifo_wr_en : out std_logic;
        msg_in : in std_logic_vector(7 downto 0 );
        RXCOMMADET : out std_logic;
        RXCHARISK : out std_logic_vector(1 downto 0 );
        msg_strobe : in std_logic_vector(1 downto 0 );
        RXNOTINTABLE : out std_logic_vector(1 downto 0 );
        bcast_strobe : out std_logic;
        RXRUNDISP : out std_logic_vector(1 downto 0 );
        TXBUFERR : out std_logic;
        RXDISPERR : out std_logic_vector(1 downto 0 );
        TXRUNDISP : out std_logic_vector(1 downto 0 );
        RXCLKCORCNT : out std_logic_vector(2 downto 0 );
        backpressure : in std_logic;
        gts_clk : out std_logic;
        l_trg : in std_logic_vector(1 downto 0 );
        RXCHARISCOMMA : out std_logic_vector(1 downto 0 );
        RXCHECKINGCRC : out std_logic;
        RXCRCERR : out std_logic;
        reset : out std_logic;
        timestamp_lsw : out std_logic_vector(15 downto 0 );
        lclk : in std_logic
        );
 
 
end RTX;
 
 
use work.all;
architecture RTX of RTX is
 
  signal g : std_logic;
  signal clear_idle : std_logic;
  signal msk1 : std_logic_vector(47 downto 0 );
  signal msk2 : std_logic_vector(47 downto 0 );
  signal outofsync : std_logic;
  signal rxdata : std_logic_vector(15 downto 0 );
  signal bclk : std_logic;
  signal TXCHARISK : std_logic_vector(1 downto 0 );
  signal msb : std_logic_vector(7 downto 0 );
  signal a_comma : std_logic;
  signal S35 : std_logic;
  signal O : std_logic;
  signal S36 : std_logic;
  signal L1A_arrived : std_logic;
  signal I1 : std_logic;
  signal EQ : std_logic;
  signal S90 : std_logic;
  signal I2 : std_logic;
  signal tstamp_lsw : std_logic_vector(15 downto 0 );
  signal S26 : std_logic;
  signal S24 : std_logic;
  signal S44 : std_logic;
  signal a_idle : std_logic;
  signal a_ack : std_logic;
  signal S78 : std_logic_vector(7 downto 0 );
  signal nibble2 : std_logic_vector(3 downto 0 );
  signal LOOPBACK : std_logic_vector(1 downto 0 );
  signal nibble1 : std_logic_vector(3 downto 0 );
  signal TXDATA : std_logic_vector(15 downto 0 );
  signal TXBYPASS8B10B : std_logic_vector(1 downto 0 );
  signal RXRECCLK : std_logic;
  signal ts_16 : std_logic_vector(15 downto 0 );
  signal refclksel : std_logic;
  signal RXLOSSOFSYNC : std_logic_vector(1 downto 0 );
  component t_decode
      port (
            bclk : in std_logic;
            lreset : in std_logic;
            tstamp_err : out std_logic;
            fiber_in : in std_logic_vector(15 downto 0 );
            msk1 : in std_logic_vector(47 downto 0 );
            msk2 : in std_logic_vector(47 downto 0 );
            timestamp : out std_logic_vector(47 downto 0 );
            tstamp_lsw : out std_logic_vector(15 downto 0 )
            );
  end component;
  component cmd_dec
      port (
            refclksel : out std_logic;
            bcast_out : out std_logic_vector(7 downto 0 );
            DoubleErr : out std_ulogic;
            event_num : out std_logic_vector(23 downto 0 );
            MultipleErr : out std_ulogic;
            SingleErr : out std_ulogic;
            outofsync : in std_logic;
            bclk : in std_logic;
            L1A : out std_logic_vector(15 downto 0 );
            msb : in std_logic_vector(7 downto 0 );
            L1A_arrived : out std_logic;
            lreset : in std_logic;
            bcast_strobe : out std_logic;
            CheckOut : out std_logic_vector(0 to 3 );
            reset : out std_logic
            );
  end component;
  component MGT_custom
      port (
            CONFIGENABLE : in std_logic;
            CONFIGIN : in std_logic;
            ENMCOMMAALIGN : in std_logic;
            ENPCOMMAALIGN : in std_logic;
            ENCHANSYNC : in std_logic;
            LOOPBACK : in std_logic_vector(1 downto 0 );
            POWERDOWN : in std_logic;
            REFCLK : in std_logic;
            REFCLK2 : in std_logic;
            REFCLKSEL : in std_logic;
            BREFCLK : in std_logic;
            BREFCLK2 : in std_logic;
            RXN : in std_logic;
            RXP : in std_logic;
            RXPOLARITY : in std_logic;
            RXRESET : in std_logic;
            RXUSRCLK : in std_logic;
            RXUSRCLK2 : in std_logic;
            TXBYPASS8B10B : in std_logic_vector(1 downto 0 );
            TXCHARDISPMODE : in std_logic_vector(1 downto 0 );
            TXCHARDISPVAL : in std_logic_vector(1 downto 0 );
            TXCHARISK : in std_logic_vector(1 downto 0 );
            TXDATA : in std_logic_vector(15 downto 0 );
            TXFORCECRCERR : in std_logic;
            TXINHIBIT : in std_logic;
            TXPOLARITY : in std_logic;
            TXRESET : in std_logic;
            TXUSRCLK : in std_logic;
            TXUSRCLK2 : in std_logic;
            CHBONDDONE : out std_logic;
            CONFIGOUT : out std_logic;
            RXBUFSTATUS : out std_logic_vector(1 downto 0 );
            RXCHARISCOMMA : out std_logic_vector(1 downto 0 );
            RXCHARISK : out std_logic_vector(1 downto 0 );
            RXCHECKINGCRC : out std_logic;
            RXCLKCORCNT : out std_logic_vector(2 downto 0 );
            RXCOMMADET : out std_logic;
            RXCRCERR : out std_logic;
            RXDATA : out std_logic_vector(15 downto 0 );
            RXDISPERR : out std_logic_vector(1 downto 0 );
            RXLOSSOFSYNC : out std_logic_vector(1 downto 0 );
            RXNOTINTABLE : out std_logic_vector(1 downto 0 );
            RXREALIGN : out std_logic;
            RXRECCLK : out std_logic;
            RXRUNDISP : out std_logic_vector(1 downto 0 );
            TXBUFERR : out std_logic;
            TXKERR : out std_logic_vector(1 downto 0 );
            TXN : out std_logic;
            TXP : out std_logic;
            TXRUNDISP : out std_logic_vector(1 downto 0 )
            );
  end component;
  component cmd_enc
      port (
            DoubleErr : out std_ulogic;
            l_tag : in std_logic_vector(7 downto 0 );
            TXDATA : out std_logic_vector(15 downto 0 );
            MultipleErr : out std_ulogic;
            msg_in : in std_logic_vector(7 downto 0 );
            SingleErr : out std_ulogic;
            bclk : in std_logic;
            msg_strobe : in std_logic_vector(1 downto 0 );
            lreset : in std_logic;
            backpressure : in std_logic;
            l_trg : in std_logic_vector(1 downto 0 );
            DataCorr : out std_logic_vector(0 to 7 );
            a_comma : in std_logic;
            clear_idle : out std_logic;
            a_ack : out std_logic;
            a_idle : in std_logic;
            ts_16 : in std_logic_vector(15 downto 0 )
            );
  end component;
  component L1A_fifo_ctrl
      port (
            bclk : in std_logic;
            lreset : in std_logic;
            L1A_fifo_wr_en : out std_logic;
            L1A_fifo_full : in std_logic;
            L1A_arrived : in std_logic
            );
  end component;
  component auto_cmd
      port (
            a_comma : out std_logic;
            bclk : in std_logic;
            lreset : in std_logic;
            clear_idle : in std_logic;
            a_ack : in std_logic;
            a_idle : out std_logic
            );
  end component;
  component lut_a
      port (
            A : in std_logic_vector(3 downto 0 );
            SPO : out std_logic_vector(47 downto 0 )
            );
  end component;
  component lut_b
      port (
            A : in std_logic_vector(3 downto 0 );
            SPO : out std_logic_vector(47 downto 0 )
            );
  end component;
 
  -- Start Configuration Specification
  -- ++ for all : t_decode use entity work.t_decode(t_dec);
  -- ++ for all : cmd_dec use entity work.cmd_dec(cmd_dec);
  -- ++ for all : MGT_custom use entity work.MGT_custom(STRUCT);
  -- ++ for all : cmd_enc use entity work.cmd_enc(cmd_enc);
  -- ++ for all : L1A_fifo_ctrl use entity work.L1A_fifo_ctrl(L1A_fifo_ctrl);
  -- ++ for all : auto_cmd use entity work.auto_cmd(auto_cmd);
  -- ++ for all : lut_a use entity work.lut_a(lut_a_a);
  -- ++ for all : lut_b use entity work.lut_b(lut_b_a);
  -- End Configuration Specification
 
begin
 
  inst_t_decode: t_decode
    port map (
              bclk => bclk,
              lreset => lreset,
              tstamp_err => tstamp_err,
              fiber_in => rxdata(15 downto 0),
              msk1 => msk1(47 downto 0),
              msk2 => msk2(47 downto 0),
              timestamp => timestamp(47 downto 0),
              tstamp_lsw => tstamp_lsw(15 downto 0)
              );
 
  inst_cmd_dec: cmd_dec
    port map (
              refclksel => refclksel,
              bcast_out => bcast_out(7 downto 0),
              DoubleErr => open,
              event_num => event_num(23 downto 0),
              MultipleErr => open,
              SingleErr => open,
              outofsync => outofsync,
              bclk => bclk,
              L1A => L1A(15 downto 0),
              msb => msb(7 downto 0),
              L1A_arrived => L1A_arrived,
              lreset => lreset,
              bcast_strobe => bcast_strobe,
              CheckOut => open,
              reset => reset
              );
 
  C12: MGT_custom
    port map (
              CONFIGENABLE => O,
              CONFIGIN => O,
              ENMCOMMAALIGN => S24,
              ENPCOMMAALIGN => S24,
              ENCHANSYNC => S26,
              LOOPBACK => LOOPBACK(1 downto 0),
              POWERDOWN => S26,
              REFCLK => lclk,
              REFCLK2 => bclk,
              REFCLKSEL => refclksel,
              BREFCLK => g,
              BREFCLK2 => g,
              RXN => fiber_in_n,
              RXP => fiber_in_p,
              RXPOLARITY => S35,
              RXRESET => lreset,
              RXUSRCLK => bclk,
              RXUSRCLK2 => bclk,
              TXBYPASS8B10B => TXBYPASS8B10B(1 downto 0),
              TXCHARDISPMODE => TXBYPASS8B10B(1 downto 0),
              TXCHARDISPVAL => TXBYPASS8B10B(1 downto 0),
              TXCHARISK => TXCHARISK(1 downto 0),
              TXDATA => TXDATA(15 downto 0),
              TXFORCECRCERR => S44,
              TXINHIBIT => S44,
              TXPOLARITY => S44,
              TXRESET => lreset,
              TXUSRCLK => bclk,
              TXUSRCLK2 => bclk,
              CHBONDDONE => CHBONDDONE,
              CONFIGOUT => CONFIGOUT,
              RXBUFSTATUS => RXBUFSTATUS(1 downto 0),
              RXCHARISCOMMA => RXCHARISCOMMA(1 downto 0),
              RXCHARISK => RXCHARISK(1 downto 0),
              RXCHECKINGCRC => RXCHECKINGCRC,
              RXCLKCORCNT => RXCLKCORCNT(2 downto 0),
              RXCOMMADET => RXCOMMADET,
              RXCRCERR => RXCRCERR,
              RXDATA => rxdata(15 downto 0),
              RXDISPERR => RXDISPERR(1 downto 0),
              RXLOSSOFSYNC => RXLOSSOFSYNC(1 downto 0),
              RXNOTINTABLE => RXNOTINTABLE(1 downto 0),
              RXREALIGN => RXREALIGN,
              RXRECCLK => RXRECCLK,
              RXRUNDISP => RXRUNDISP(1 downto 0),
              TXBUFERR => TXBUFERR,
              TXKERR => TXKERR(1 downto 0),
              TXN => fiber_out_n,
              TXP => fiber_out_p,
              TXRUNDISP => TXRUNDISP(1 downto 0)
              );
 
  inst_cmd_enc: cmd_enc
    port map (
              DoubleErr => open,
              l_tag => l_tag(7 downto 0),
              TXDATA => TXDATA(15 downto 0),
              MultipleErr => open,
              msg_in => msg_in(7 downto 0),
              SingleErr => open,
              bclk => bclk,
              msg_strobe => msg_strobe(1 downto 0),
              lreset => lreset,
              backpressure => backpressure,
              l_trg => l_trg(1 downto 0),
              DataCorr => open,
              a_comma => a_comma,
              clear_idle => clear_idle,
              a_ack => a_ack,
              a_idle => a_idle,
              ts_16 => ts_16(15 downto 0)
              );
 
  inst_L1A_fifo_ctrl: L1A_fifo_ctrl
    port map (
              bclk => bclk,
              lreset => lreset,
              L1A_fifo_wr_en => L1A_fifo_wr_en,
              L1A_fifo_full => L1A_fifo_full,
              L1A_arrived => L1A_arrived
              );
 
  inst_auto_cmd: auto_cmd
    port map (
              a_comma => a_comma,
              bclk => bclk,
              lreset => lreset,
              clear_idle => clear_idle,
              a_ack => a_ack,
              a_idle => a_idle
              );
 
  inst_lut_a: lut_a
    port map (
              A => nibble1(3 downto 0),
              SPO => msk1(47 downto 0)
              );
 
  inst_lut_b: lut_b
    port map (
              A => nibble2(3 downto 0),
              SPO => msk2(47 downto 0)
              );
 
  nibble2(3 downto 0) < = rxdata(3 downto 0);
  msb(7 downto 0) < = rxdata(15 downto 8);
  nibble1(3 downto 0) < = rxdata(3 downto 0);
 
  gclk < = RXRECCLK;
  gts_clk < = RXRECCLK;
  bclk < = RXRECCLK;
 
      O < = '0';
 
      S24 < = '1';
 
      S26 < = '0';
 
  LOOPBACK(1) < = S26;
  LOOPBACK(0) < = S26;
 
      g < = '0';
 
      S35 < = '0';
 
      S36 < = '0';
 
  TXBYPASS8B10B(1) < = S36;
  TXBYPASS8B10B(0) < = S36;
 
      S44 < = '0';
 
 
  process (TXDATA , S78)
   begin
      if ((TXDATA(15 downto 8)) = (S78(7 downto 0))) then
        EQ < = '1';
      else
        EQ < = '0';
      end if;
  end process;
 
 
  S78(7 downto 0) < = "00111100";
 
 
  TXCHARISK(1) < = EQ;
  TXCHARISK(0) < = S90;
 
      S90 < = '0';
 
   outofsync < = ( I1) or ( I2);
 
 
  I1 < = RXLOSSOFSYNC(1);
  I2 < = RXLOSSOFSYNC(0);
 
  timestamp_lsw(15 downto 0) < = tstamp_lsw(15 downto 0);
  ts_16(15 downto 0) < = tstamp_lsw(15 downto 0);
end RTX;
----------------------------------------------------
--  
--  Library Name :  GTS
--  Unit    Name :  T_valreject_ctrl
--  Unit    Type :  State Machine
--  
------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
 
 
entity T_valreject_ctrl is
  port (
        gclk : in std_logic;
        reset : in std_logic;
        trigger_validation : out std_logic;
        trigger_rejection : out std_logic;
        val_rej_tag : out std_logic_vector(7 downto 0 );
        validate : in std_logic;
        rejecta : in std_logic;
        validate_ack : out std_logic;
        reject_ack : out std_logic;
        vaLreject_tag : in std_logic_vector(47 downto 0 );
        tag_strobe : out std_logic;
        ev_num : in std_logic_vector(23 downto 0 )
        );
 
end T_valreject_ctrl;
 
 
architecture T_valreject_ctrl of T_valreject_ctrl is
 
  type visual_S0_states is (S0, S1, S10, S11, S12, S13, S14, S15, S16, S17, S2,
                            S3, S4, S5, S6, S7, S8, S9);
  signal visual_S0_current : visual_S0_states;
 
 
begin
 
 
 
  -- Synchronous process
  T_valreject_ctrl_S0:
  process (gclk, reset)
  begin
 
    if (reset = '1') then
      tag_strobe< ='0';
      reject_ack< ='0';
      validate_ack< ='0';
      trigger_rejection< ='0';
      trigger_validation< ='0';
      val_rej_tag< =(others=>'0');
      visual_S0_current < = S0;
    elsif (gclk'event and gclk = '1') then
 
      case visual_S0_current is
        when S0 =>
          if (rejecta = '1') then
            trigger_rejection< ='1';
            val_rej_tag< =valreject_tag(47 downto 40);
            tag_strobe< ='1';
            visual_S0_current < = S1;
          elsif (validate = '1') then
            trigger_validation< ='1';
            val_rej_tag< =valreject_tag(47 downto 40);
            tag_strobe< ='1';
            visual_S0_current < = S6;
          else
            visual_S0_current < = S0;
          end if;
 
        when S1 =>
          trigger_rejection< ='0';
          val_rej_tag< =valreject_tag(39 downto 32);
          visual_S0_current < = S2;
 
        when S10 =>
          val_rej_tag< =valreject_tag(7 downto 0);
          visual_S0_current < = S12;
 
        when S11 =>
          val_rej_tag< =(others=>'0');
          tag_strobe< ='0';
          visual_S0_current < = S13;
 
        when S12 =>
          val_rej_tag< =ev_num(23 downto 16);
          visual_S0_current < = S15;
 
        when S13 =>
          if (rejecta = '0') then
            tag_strobe< ='0';
            reject_ack< ='0';
            validate_ack< ='0';
            trigger_rejection< ='0';
            trigger_validation< ='0';
            val_rej_tag< =(others=>'0');
            visual_S0_current < = S0;
          else
            visual_S0_current < = S13;
          end if;
 
        when S14 =>
          if (validate = '0') then
            tag_strobe< ='0';
            reject_ack< ='0';
            validate_ack< ='0';
            trigger_rejection< ='0';
            trigger_validation< ='0';
            val_rej_tag< =(others=>'0');
            visual_S0_current < = S0;
          else
            visual_S0_current < = S14;
          end if;
 
        when S15 =>
          val_rej_tag< =ev_num(15 downto 8);
          visual_S0_current < = S16;
 
        when S16 =>
          val_rej_tag< =ev_num(7 downto 0);
          validate_ack< ='1';
          visual_S0_current < = S17;
 
        when S17 =>
          val_rej_tag< =(others=>'0');
          tag_strobe< ='0';
          visual_S0_current < = S14;
 
        when S2 =>
          val_rej_tag< =valreject_tag(31 downto 24);
          visual_S0_current < = S3;
 
        when S3 =>
          val_rej_tag< =valreject_tag(23 downto 16);
          visual_S0_current < = S4;
 
        when S4 =>
          val_rej_tag< =valreject_tag(15 downto 8);
          visual_S0_current < = S5;
 
        when S5 =>
          val_rej_tag< =valreject_tag(7 downto 0);
          reject_ack< ='1';
          visual_S0_current < = S11;
 
        when S6 =>
          trigger_validation< ='0';
          val_rej_tag< =valreject_tag(39 downto 32);
          visual_S0_current < = S7;
 
        when S7 =>
          val_rej_tag< =valreject_tag(31 downto 24);
          visual_S0_current < = S8;
 
        when S8 =>
          val_rej_tag< =valreject_tag(23 downto 16);
          visual_S0_current < = S9;
 
        when S9 =>
          val_rej_tag< =valreject_tag(15 downto 8);
          visual_S0_current < = S10;
 
        when others =>
 
          tag_strobe< ='0';
          reject_ack< ='0';
          validate_ack< ='0';
          trigger_rejection< ='0';
          trigger_validation< ='0';
          val_rej_tag< =(others=>'0');
          visual_S0_current < = S0;
      end case;
    end if;
  end process T_valreject_ctrl_S0;
 
end T_valreject_ctrl;
----------------------------------------------------
--  
--  Library Name :  GTS
--  Unit    Name :  trigger_match
--  Unit    Type :  State Machine
--  
------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.NUMERIC_STD.all;
library synplify;
use synplify.attributes.all;
 
 
entity trigger_match is
  port (
        L1A_fifo_rd_en : out std_logic;
        gclk : in std_logic;
        reset : in std_logic;
        L1A_fifo_empty : in std_logic;
        L1A_fifo_rd_data_count : in std_logic_vector(5 downto 0 );
        L1A_fifo_wr_data_count : in std_logic_vector(5 downto 0 );
        T_request_mem_empty : in std_logic;
        T_request_mem_dout : in std_logic_vector(47 downto 0 );
        validate : out std_logic;
        rejecta : out std_logic;
        validate_ack : in std_logic;
        reject_ack : in std_logic;
        timestamp_lsw : in std_logic_vector(15 downto 0 );
        vaLreject_tag : out std_logic_vector(47 downto 0 );
        checkaddr : out std_logic_vector(4 downto 0 );
        storeaddr : out std_logic_vector(4 downto 0 );
        store_en : out std_logic;
        clear : out std_logic_vector(47 downto 0 );
        clear_en : out std_logic;
        reject_window : in std_logic_vector(15 downto 0 );
        L1A_tag : in std_logic_vector(15 downto 0 )
        );
 
end trigger_match;
 
 
architecture trigger_match of trigger_match is
 
  constant REJECT_TIME : unsigned(16 downto 0 ) := "00000010000000000";  --  400
  constant MOD_MASK : unsigned(16 downto 0 ) := "10000000000000000";  --  1**16
  signal match_high : unsigned(16 downto 0 );
  signal match_low : unsigned(16 downto 0 );
  signal event_time : unsigned(16 downto 0 );
  signal L1A_time : unsigned(16 downto 0 );
  signal trigger_matched : std_logic;
  signal ev_discard : std_logic;
  signal max_elapsed : unsigned(16 downto 0 );
  signal elapsed : unsigned(16 downto 0 );
  signal lcnt : std_logic_vector(4 downto 0 );
 
  type visual_RST_S_states is (RST_S, M1, M2, check_l1a_fifo, match_start,
                               reject_start, S31, S14, S23, S29, S30, S32, S33,
                               S34, S36, S20, S15, S16, S17, S18, S19, S21, S22,
                               S24, S11, S12, S13, S25, S28, S26, S27, S35);
  signal visual_RST_S_current : visual_RST_S_states;
 
 
begin
 
 
 
  -- Synchronous process
  trigger_match_RST_S:
  process (gclk, reset)
  begin
 
    if (reset = '1') then
      trigger_matched< ='0';
      ev_discard< ='0';
      L1A_fifo_rd_en< ='0';
      visual_RST_S_current < = RST_S;
    elsif (gclk'event and gclk = '1') then
 
      case visual_RST_S_current is
        when RST_S =>
          lcnt< ="11111";
          clear_en< ='0';
          clear< =(others=>'0');
          store_en< ='0';
          visual_RST_S_current < = S28;
 
        when M1 =>
          L1A_time< =unsigned('0' & L1A_tag);
          visual_RST_S_current < = M2;
 
        when M2 =>
          if (T_request_mem_empty = '0') then
            lcnt< ="11111";
            clear_en< ='0';
            clear< =(others=>'0');
            store_en< ='0';
            visual_RST_S_current < = S20;
          else
            visual_RST_S_current < = check_l1a_fifo;
          end if;
 
        when check_l1a_fifo =>
          if (L1A_fifo_empty = '0') then
            L1A_fifo_rd_en< ='1';
            visual_RST_S_current < = match_start;
          else
            visual_RST_S_current < = reject_start;
          end if;
 
        when match_start =>
          trigger_matched< ='0';
          ev_discard< ='0';
          L1A_fifo_rd_en< ='0';
          visual_RST_S_current < = M1;
 
        when reject_start =>
          if (T_request_mem_empty = '0') then
            lcnt< ="11111";
            clear_en< ='0';
            clear< =(others=>'0');
            store_en< ='0';
            visual_RST_S_current < = S31;
          else
            visual_RST_S_current < = check_l1a_fifo;
          end if;
 
        when S31 =>
          lcnt< =std_logic_vector(unsigned(lcnt)+1);
          clear_en< ='0';
          store_en< ='0';
          visual_RST_S_current < = S32;
 
        when S14 =>
          max_elapsed < =(unsigned('0' & timestamp_lsw) - event_time) mod MOD_MASK;
          visual_RST_S_current < = S23;
 
        when S23 =>
          if (max_elapsed >= (
              UNSIGNED ('0' & reject_window))) then
            visual_RST_S_current < = S34;
          else
            lcnt< =std_logic_vector(unsigned(lcnt)+1);
            clear_en< ='0';
            store_en< ='0';
            visual_RST_S_current < = S32;
          end if;
 
        when S29 =>
          if (reject_ack = '1') then
            rejecta< ='0';
            clear_en< ='1';
            store_en< ='1';
            visual_RST_S_current < = S30;
          else
            visual_RST_S_current < = S29;
          end if;
 
        when S30 =>
          lcnt< =std_logic_vector(unsigned(lcnt)+1);
          clear_en< ='0';
          store_en< ='0';
          visual_RST_S_current < = S32;
 
        when S32 =>
          if (lcnt = "10000" or L1A_fifo_empty = '0') then
            visual_RST_S_current < = check_l1a_fifo;
          else
            checkaddr< =lcnt;
            visual_RST_S_current < = S33;
          end if;
 
        when S33 =>
          visual_RST_S_current < = S36;
 
        when S34 =>
          vaLreject_tag< =T_request_mem_dout;
          rejecta< ='1';
          storeaddr< =lcnt;
          visual_RST_S_current < = S29;
 
        when S36 =>
          if (T_request_mem_dout =
              "000000000000000000000000000000000000000000000000") then
            lcnt< =std_logic_vector(unsigned(lcnt)+1);
            clear_en< ='0';
            store_en< ='0';
            visual_RST_S_current < = S32;
          else
            event_time< =unsigned('0' & T_request_mem_dout(15 downto 0));
            visual_RST_S_current < = S14;
          end if;
 
        when S20 =>
          lcnt< =std_logic_vector(unsigned(lcnt)+1);
          clear_en< ='0';
          store_en< ='0';
          visual_RST_S_current < = S21;
 
        when S15 =>
          if (trigger_matched = '1') then
            vaLreject_tag< =T_request_mem_dout;
            validate< ='1';
            storeaddr< =lcnt;
            visual_RST_S_current < = S17;
          elsif (ev_discard = '1') then
            vaLreject_tag< =T_request_mem_dout;
            rejecta< ='1';
            storeaddr< =lcnt;
            visual_RST_S_current < = S18;
          else
            lcnt< =std_logic_vector(unsigned(lcnt)+1);
            clear_en< ='0';
            store_en< ='0';
            visual_RST_S_current < = S21;
          end if;
 
        when S16 =>
          lcnt< =std_logic_vector(unsigned(lcnt)+1);
          clear_en< ='0';
          store_en< ='0';
          visual_RST_S_current < = S21;
 
        when S17 =>
          if (validate_ack = '1') then
            validate< ='0';
            clear_en< ='1';
            store_en< ='1';
            visual_RST_S_current < = S16;
          else
            visual_RST_S_current < = S17;
          end if;
 
        when S18 =>
          if (reject_ack = '1') then
            rejecta< ='0';
            clear_en< ='1';
            store_en< ='1';
            visual_RST_S_current < = S19;
          else
            visual_RST_S_current < = S18;
          end if;
 
        when S19 =>
          lcnt< =std_logic_vector(unsigned(lcnt)+1);
          clear_en< ='0';
          store_en< ='0';
          visual_RST_S_current < = S21;
 
        when S21 =>
          if (lcnt = "10000") then
            visual_RST_S_current < = check_l1a_fifo;
          else
            checkaddr< = lcnt;
            visual_RST_S_current < = S22;
          end if;
 
        when S22 =>
          visual_RST_S_current < = S24;
 
        when S24 =>
          if (T_request_mem_dout =
              "000000000000000000000000000000000000000000000000") then
            lcnt< =std_logic_vector(unsigned(lcnt)+1);
            clear_en< ='0';
            store_en< ='0';
            visual_RST_S_current < = S21;
          else
            event_time< =unsigned('0' & T_request_mem_dout(15 downto 0));
            trigger_matched < = '0';
            ev_discard < = '0';
            visual_RST_S_current < = S11;
          end if;
 
        when S11 =>
          if (L1A_time = event_time) then
            trigger_matched < = '1';
            visual_RST_S_current < = S12;
          else
            max_elapsed < =(unsigned('0' & timestamp_lsw) - event_time) mod MOD_MASK;
            visual_RST_S_current < = S13;
          end if;
 
        when S12 =>
          visual_RST_S_current < = S15;
 
        when S13 =>
          if (max_elapsed >= (
              UNSIGNED ('0' & reject_window))) then
            ev_discard < ='1';
            visual_RST_S_current < = S25;
          else
            visual_RST_S_current < = S15;
          end if;
 
        when S25 =>
          visual_RST_S_current < = S15;
 
        when S28 =>
          lcnt< =std_logic_vector(unsigned(lcnt)+1);
          clear_en< ='0';
          store_en< ='0';
          visual_RST_S_current < = S35;
 
        when S26 =>
          clear_en< ='1';
          store_en< ='1';
          visual_RST_S_current < = S27;
 
        when S27 =>
          lcnt< =std_logic_vector(unsigned(lcnt)+1);
          clear_en< ='0';
          store_en< ='0';
          visual_RST_S_current < = S35;
 
        when S35 =>
          if (lcnt = "10000") then
            visual_RST_S_current < = check_l1a_fifo;
          else
            storeaddr< =lcnt;
            visual_RST_S_current < = S26;
          end if;
 
        when others =>
 
          trigger_matched< ='0';
          ev_discard< ='0';
          L1A_fifo_rd_en< ='0';
          visual_RST_S_current < = RST_S;
      end case;
    end if;
  end process trigger_match_RST_S;
 
end trigger_match;
----------------------------------------------------
--  
--  Library Name :  GTS
--  Unit    Name :  GTS_top
--  Unit    Type :  Block Diagram
--  
------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.STD_LOGIC_UNSIGNED.all;
library synplify;
use synplify.attributes.all;
 
 
entity GTS_top is
  port (
        bcast_out : out std_logic_vector(7 downto 0 );
        fiber_in_n : in std_logic;
        fiber_in_p : in std_logic;
        fiber_out_n : out std_logic;
        fiber_out_p : out std_logic;
        trigger_rejection : out std_logic;
        tstamp_err : out std_logic;
        msg_in : in std_logic_vector(7 downto 0 );
        trigger_validation : out std_logic;
        val_rej_tag : out std_logic_vector(7 downto 0 );
        local_tag : out std_logic_vector(7 downto 0 );
        lreset : in std_logic;
        bcast_strobe : out std_logic;
        msg_strobe : in std_logic_vector(1 downto 0 );
        backpressure : in std_logic;
        local_trigger : out std_logic_vector(1 downto 0 );
        tag_strobe : out std_logic;
        lt_strobe : out std_logic;
        gts_clk : out std_logic;
        trigger_request : in std_logic_vector(1 downto 0 );
        reject_window : in std_logic_vector(15 downto 0 );
        lclk : in std_logic
        );
 
 
end GTS_top;
 
 
use work.all;
architecture GTS_top of GTS_top is
 
  signal T_request_wr_data_count : std_logic_vector(4 downto 0 );
  signal timestamp_lsw : std_logic_vector(15 downto 0 );
  signal validation : std_logic_vector(39 downto 0 );
  signal t : std_logic_vector(47 downto 0 );
  signal T_request_mem_empty : std_logic;
  signal l_tag : std_logic_vector(7 downto 0 );
  signal rejecta : std_logic;
  signal gclk : std_logic;
  signal event_num : std_logic_vector(23 downto 0 );
  signal L1A_fifo_full : std_logic;
  signal ltag : std_logic_vector(7 downto 0 );
  signal L1A_fifo_wr_en : std_logic;
  signal L1A_tag : std_logic_vector(15 downto 0 );
  signal L1A_fifo_wr_data_count : std_logic_vector(5 downto 0 );
  signal storeaddr : std_logic_vector(4 downto 0 );
  signal L1A : std_logic_vector(15 downto 0 );
  signal T_request_mem_dout : std_logic_vector(47 downto 0 );
  signal L1A_fifo_empty : std_logic;
  signal freeaddr : std_logic_vector(4 downto 0 );
  signal L1A_fifo_rd_data_count : std_logic_vector(5 downto 0 );
  signal store_en : std_logic;
  signal clear : std_logic_vector(47 downto 0 );
  signal reject_ack : std_logic;
  signal rd_en : std_logic;
  signal L1A_fifo_rd_en : std_logic;
  signal validate_ack : std_logic;
  signal L1A_fifo_dout : std_logic_vector(39 downto 0 );
  signal clear_en : std_logic;
  signal checkaddr : std_logic_vector(4 downto 0 );
  signal vaLreject_tag : std_logic_vector(47 downto 0 );
  signal l_trg : std_logic_vector(1 downto 0 );
  signal T_request_mem_full : std_logic;
  signal validate : std_logic;
  signal ev_num : std_logic_vector(23 downto 0 );
  signal timestamp : std_logic_vector(47 downto 0 );
  signal reset : std_logic;
  signal T_request_mem_wr_en : std_logic;
  signal ltrg : std_logic_vector(1 downto 0 );
  component trigger_match
      port (
            L1A_fifo_rd_en : out std_logic;
            gclk : in std_logic;
            reset : in std_logic;
            L1A_fifo_empty : in std_logic;
            L1A_fifo_rd_data_count : in std_logic_vector(5 downto 0 );
            L1A_fifo_wr_data_count : in std_logic_vector(5 downto 0 );
            T_request_mem_empty : in std_logic;
            T_request_mem_dout : in std_logic_vector(47 downto 0 );
            validate : out std_logic;
            rejecta : out std_logic;
            validate_ack : in std_logic;
            reject_ack : in std_logic;
            timestamp_lsw : in std_logic_vector(15 downto 0 );
            vaLreject_tag : out std_logic_vector(47 downto 0 );
            checkaddr : out std_logic_vector(4 downto 0 );
            storeaddr : out std_logic_vector(4 downto 0 );
            store_en : out std_logic;
            clear : out std_logic_vector(47 downto 0 );
            clear_en : out std_logic;
            reject_window : in std_logic_vector(15 downto 0 );
            L1A_tag : in std_logic_vector(15 downto 0 )
            );
  end component;
  component T_valreject_ctrl
      port (
            gclk : in std_logic;
            reset : in std_logic;
            trigger_validation : out std_logic;
            trigger_rejection : out std_logic;
            val_rej_tag : out std_logic_vector(7 downto 0 );
            validate : in std_logic;
            rejecta : in std_logic;
            validate_ack : out std_logic;
            reject_ack : out std_logic;
            vaLreject_tag : in std_logic_vector(47 downto 0 );
            tag_strobe : out std_logic;
            ev_num : in std_logic_vector(23 downto 0 )
            );
  end component;
  component RTX
      port (
            tstamp_err : out std_logic;
            L1A : out std_logic_vector(15 downto 0 );
            lreset : in std_logic;
            timestamp : out std_logic_vector(47 downto 0 );
            RXBUFSTATUS : out std_logic_vector(1 downto 0 );
            bcast_out : out std_logic_vector(7 downto 0 );
            fiber_in_n : in std_logic;
            fiber_in_p : in std_logic;
            RXREALIGN : out std_logic;
            fiber_out_n : out std_logic;
            l_tag : in std_logic_vector(7 downto 0 );
            TXKERR : out std_logic_vector(1 downto 0 );
            fiber_out_p : out std_logic;
            gclk : out std_logic;
            CONFIGOUT : out std_logic;
            CHBONDDONE : out std_logic;
            L1A_fifo_full : in std_logic;
            event_num : out std_logic_vector(23 downto 0 );
            L1A_fifo_wr_en : out std_logic;
            msg_in : in std_logic_vector(7 downto 0 );
            RXCOMMADET : out std_logic;
            RXCHARISK : out std_logic_vector(1 downto 0 );
            msg_strobe : in std_logic_vector(1 downto 0 );
            RXNOTINTABLE : out std_logic_vector(1 downto 0 );
            bcast_strobe : out std_logic;
            RXRUNDISP : out std_logic_vector(1 downto 0 );
            TXBUFERR : out std_logic;
            RXDISPERR : out std_logic_vector(1 downto 0 );
            TXRUNDISP : out std_logic_vector(1 downto 0 );
            RXCLKCORCNT : out std_logic_vector(2 downto 0 );
            backpressure : in std_logic;
            gts_clk : out std_logic;
            l_trg : in std_logic_vector(1 downto 0 );
            RXCHARISCOMMA : out std_logic_vector(1 downto 0 );
            RXCHECKINGCRC : out std_logic;
            RXCRCERR : out std_logic;
            reset : out std_logic;
            timestamp_lsw : out std_logic_vector(15 downto 0 );
            lclk : in std_logic
            );
  end component;
  component T_request_ctrl
      port (
            T_request_mem_full : in std_logic;
            trigger_request : in std_logic_vector(1 downto 0 );
            T_request_mem_wr_en : out std_logic;
            gclk : in std_logic;
            reset : in std_logic;
            timestamp : in std_logic_vector(47 downto 0 );
            t : out std_logic_vector(47 downto 0 );
            rd_en : out std_logic;
            T_request_wr_data_count : in std_logic_vector(4 downto 0 );
            lt_strobe : out std_logic;
            ltrg : out std_logic_vector(1 downto 0 );
            ltag : out std_logic_vector(7 downto 0 )
            );
  end component;
  component fifo_freelist
      port (
            din : in std_logic_vector(4 downto 0 );
            rd_clk : in std_logic;
            rd_en : in std_logic;
            rst : in std_logic;
            wr_clk : in std_logic;
            wr_en : in std_logic;
            dout : out std_logic_vector(4 downto 0 );
            empty : out std_logic;
            full : out std_logic;
            wr_data_count : out std_logic_vector(4 downto 0 )
            );
  end component;
  component dpram_tstamp
      port (
            addra : in std_logic_vector(4 downto 0 );
            addrb : in std_logic_vector(4 downto 0 );
            clka : in std_logic;
            clkb : in std_logic;
            dina : in std_logic_vector(47 downto 0 );
            dinb : in std_logic_vector(47 downto 0 );
            doutb : out std_logic_vector(47 downto 0 );
            wea : in std_logic;
            web : in std_logic
            );
  end component;
  component fifo_l1a
      port (
            din : in std_logic_vector(39 downto 0 );
            rd_clk : in std_logic;
            rd_en : in std_logic;
            rst : in std_logic;
            wr_clk : in std_logic;
            wr_en : in std_logic;
            dout : out std_logic_vector(39 downto 0 );
            empty : out std_logic;
            full : out std_logic;
            rd_data_count : out std_logic_vector(5 downto 0 );
            wr_data_count : out std_logic_vector(5 downto 0 )
            );
  end component;
 
  -- Start Configuration Specification
  -- ++ for all : trigger_match use entity work.trigger_match(trigger_match);
  -- ++ for all : T_valreject_ctrl use entity work.T_valreject_ctrl(
  -- ++   T_valreject_ctrl);
  -- ++ for all : RTX use entity work.RTX(RTX);
  -- ++ for all : T_request_ctrl use entity work.T_request_ctrl(T_request_ctrl);
  -- ++ for all : fifo_freelist use entity work.fifo_freelist(fifo_freelist_a);
  -- ++ for all : dpram_tstamp use entity work.dpram_tstamp(dpram_tstamp_a);
  -- ++ for all : fifo_l1a use entity work.fifo_l1a(fifo_l1a_a);
  -- End Configuration Specification
 
begin
 
  inst_trigger_match: trigger_match
    port map (
              L1A_fifo_rd_en => L1A_fifo_rd_en,
              gclk => gclk,
              reset => reset,
              L1A_fifo_empty => L1A_fifo_empty,
              L1A_fifo_rd_data_count => L1A_fifo_rd_data_count(5 downto 0),
              L1A_fifo_wr_data_count => L1A_fifo_wr_data_count(5 downto 0),
              T_request_mem_empty => T_request_mem_empty,
              T_request_mem_dout => T_request_mem_dout(47 downto 0),
              validate => validate,
              rejecta => rejecta,
              validate_ack => validate_ack,
              reject_ack => reject_ack,
              timestamp_lsw => timestamp_lsw(15 downto 0),
              vaLreject_tag => vaLreject_tag(47 downto 0),
              checkaddr => checkaddr(4 downto 0),
              storeaddr => storeaddr(4 downto 0),
              store_en => store_en,
              clear => clear(47 downto 0),
              clear_en => clear_en,
              reject_window => reject_window(15 downto 0),
              L1A_tag => L1A_tag(15 downto 0)
              );
 
  inst_T_valreject_ctrl: T_valreject_ctrl
    port map (
              gclk => gclk,
              reset => reset,
              trigger_validation => trigger_validation,
              trigger_rejection => trigger_rejection,
              val_rej_tag => val_rej_tag(7 downto 0),
              validate => validate,
              rejecta => rejecta,
              validate_ack => validate_ack,
              reject_ack => reject_ack,
              vaLreject_tag => vaLreject_tag(47 downto 0),
              tag_strobe => tag_strobe,
              ev_num => ev_num(23 downto 0)
              );
 
  inst_RTX: RTX
    port map (
              tstamp_err => tstamp_err,
              L1A => L1A(15 downto 0),
              lreset => lreset,
              timestamp => timestamp(47 downto 0),
              RXBUFSTATUS => open,
              bcast_out => bcast_out(7 downto 0),
              fiber_in_n => fiber_in_n,
              fiber_in_p => fiber_in_p,
              RXREALIGN => open,
              fiber_out_n => fiber_out_n,
              l_tag => l_tag(7 downto 0),
              TXKERR => open,
              fiber_out_p => fiber_out_p,
              gclk => gclk,
              CONFIGOUT => open,
              CHBONDDONE => open,
              L1A_fifo_full => L1A_fifo_full,
              event_num => event_num(23 downto 0),
              L1A_fifo_wr_en => L1A_fifo_wr_en,
              msg_in => msg_in(7 downto 0),
              RXCOMMADET => open,
              RXCHARISK => open,
              msg_strobe => msg_strobe(1 downto 0),
              RXNOTINTABLE => open,
              bcast_strobe => bcast_strobe,
              RXRUNDISP => open,
              TXBUFERR => open,
              RXDISPERR => open,
              TXRUNDISP => open,
              RXCLKCORCNT => open,
              backpressure => backpressure,
              gts_clk => gts_clk,
              l_trg => l_trg(1 downto 0),
              RXCHARISCOMMA => open,
              RXCHECKINGCRC => open,
              RXCRCERR => open,
              reset => reset,
              timestamp_lsw => timestamp_lsw(15 downto 0),
              lclk => lclk
              );
 
  inst_T_request_ctrl: T_request_ctrl
    port map (
              T_request_mem_full => T_request_mem_full,
              trigger_request => trigger_request(1 downto 0),
              T_request_mem_wr_en => T_request_mem_wr_en,
              gclk => gclk,
              reset => reset,
              timestamp => timestamp(47 downto 0),
              t => t(47 downto 0),
              rd_en => rd_en,
              T_request_wr_data_count => T_request_wr_data_count(4 downto 0),
              lt_strobe => lt_strobe,
              ltrg => ltrg(1 downto 0),
              ltag => ltag(7 downto 0)
              );
 
  inst_FIFO_FREELIST: fifo_freelist
    port map (
              din => storeaddr(4 downto 0),
              rd_clk => gclk,
              rd_en => rd_en,
              rst => reset,
              wr_clk => gclk,
              wr_en => store_en,
              dout => freeaddr(4 downto 0),
              empty => T_request_mem_full,
              full => T_request_mem_empty,
              wr_data_count => T_request_wr_data_count(4 downto 0)
              );
 
  DPRAM: dpram_tstamp
    port map (
              addra => freeaddr(4 downto 0),
              addrb => checkaddr(4 downto 0),
              clka => gclk,
              clkb => gclk,
              dina => t(47 downto 0),
              dinb => clear(47 downto 0),
              doutb => T_request_mem_dout(47 downto 0),
              wea => T_request_mem_wr_en,
              web => clear_en
              );
 
  inst_FIFO_L1A: fifo_l1a
    port map (
              din => validation(39 downto 0),
              rd_clk => gclk,
              rd_en => L1A_fifo_rd_en,
              rst => reset,
              wr_clk => gclk,
              wr_en => L1A_fifo_wr_en,
              dout => L1A_fifo_dout(39 downto 0),
              empty => L1A_fifo_empty,
              full => L1A_fifo_full,
              rd_data_count => L1A_fifo_rd_data_count(5 downto 0),
              wr_data_count => L1A_fifo_wr_data_count(5 downto 0)
              );
 
  l_trg(1 downto 0) < = ltrg(1 downto 0);
  local_trigger(1 downto 0) < = ltrg(1 downto 0);
 
  local_tag(7 downto 0) < = ltag(7 downto 0);
  l_tag(7 downto 0) < = ltag(7 downto 0);
 
  validation(39 downto 16) < = event_num(23 downto 0);
  validation(15 downto 0) < = L1A(15 downto 0);
 
  L1A_tag(15 downto 0) < = L1A_fifo_dout(15 downto 0);
  ev_num(23 downto 0) < = L1A_fifo_dout(39 downto 16);
end GTS_top;